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1. WO2004114399 - SUBSTRATE ENGINEERING FOR OPTIMUM CMOS DEVICE PERFORMANCE

Publication Number WO/2004/114399
Publication Date 29.12.2004
International Application No. PCT/EP2004/050879
International Filing Date 25.05.2004
IPC
H01L 21/8238 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8238Complementary field-effect transistors, e.g. CMOS
CPC
H01L 21/823807
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8238Complementary field-effect transistors, e.g. CMOS
823807with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
Applicants
  • INTERNATIONAL BUSINESS MACHINES CORPORATION [US]/[US] (AllExceptUS)
  • IBM UNITED KINGDOM LIMITED [GB]/[GB] (MG)
  • CHAN, Victor [CN]/[US] (UsOnly)
  • LEONG, Meikie [PT]/[US] (UsOnly)
  • YANG, Min [CN]/[US] (UsOnly)
Inventors
  • CHAN, Victor
  • LEONG, Meikie
  • YANG, Min
Agents
  • FOURNIER, Kevin, John
Priority Data
10/604,00320.06.2003US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) SUBSTRATE ENGINEERING FOR OPTIMUM CMOS DEVICE PERFORMANCE
(FR) INGENIERIE DE SUBSTRAT POUR UNE EFFICACITE OPTIMALE DE DISPOSITIF CMOS
Abstract
(EN) An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a <001> direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a <110> direction and the at least one NFET has a current flow in a <100> direction. The <110> direction is perpendicular to the <100> direction. A method of fabricating such as integrated semiconductor structure is also provided.
(FR) L'invention concerne une structure semi-conductrice intégrée possédant différents types de dispositifs semi-conducteurs complémentaires à l'oxyde de métal (CMOS), à savoir, des transistors à effet de champ de type P (PFET) et des transistors à effet de champ de type N (NFET), situés sur un substrat semi-conducteur, chaque dispositif CMOS étant fabriqué de telle manière que la circulation du courant pour chaque dispositif est optimale. Plus spécifiquement, ladite structure comporte un substrat semi-conducteur possédant une orientation superficielle (110) et un pointage d'encoche dans une direction <001> de la circulation du courant et au moins un PFET et au moins un NFET situés sur le substrat semi-conducteur. Ledit PFET possède une circulation du courant dans une direction <110> et au moins un NFET possède une circulation du courant dans une direction <100>. La direction <110> est perpendiculaire à la direction <100>. Cette invention a aussi trait à un procédé de fabrication d'une telle structure semi-conductrice intégrée.
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