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1. WO2004114396 - INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT DEVICES

Publication Number WO/2004/114396
Publication Date 29.12.2004
International Application No. PCT/EP2004/051131
International Filing Date 16.06.2004
Chapter 2 Demand Filed 21.04.2005
IPC
H01L 21/768 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
CPC
H01L 21/31144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31144using masks
H01L 21/768
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
H01L 21/76804
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76804by forming tapered via holes
H01L 21/76808
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76807for dual damascene structures
76808involving intermediate temporary filling with material
Applicants
  • INTERNATIONAL BUSINESS MACHINES CORPORATION [US]/[US] (AllExceptUS)
  • IBM UNITED KINGDOM LIMITED [GB]/[GB] (MG)
  • WILLE, William [US]/[US] (UsOnly)
  • EDELSTEIN, Daniel [US]/[US] (UsOnly)
  • COTE, William [US]/[US] (UsOnly)
  • BIOLSI, Peter [US]/[US] (UsOnly)
  • FRITCHE, John [US]/[US] (UsOnly)
  • UPHAM, Allan [US]/[US] (UsOnly)
Inventors
  • WILLE, William
  • EDELSTEIN, Daniel
  • COTE, William
  • BIOLSI, Peter
  • FRITCHE, John
  • UPHAM, Allan
Agents
  • LITHERLAND, David, Peter
Priority Data
10/604,05624.06.2003US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT DEVICES
(FR) STRUCTURES D'INTERCONNEXION DANS DES DISPOSITIFS DE CIRCUITS INTEGRES
Abstract
(EN) This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material (13), then the planarizing material (16) is deposited in the vias and on the dielectric material, and the barrier material (17) is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material (19), etched through the barrier material into the. planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.
(FR) La présente invention concerne la réalisation de structures d'interconnexion à damasquinage double dans des dispositifs de circuits intégrés. De façon spécifique, l'invention concerne un procédé pour constituer une structure à damasquinage simple ou double dans un film mince diélectrique à faible k, au moyen d'un matériau de planarisation et d'un matériau de barrière de diffusion. Dans un mode de réalisation préféré de ce procédé pour produire un damasquinage double, les trous d'interconnexion sont formés tout d'abord dans le matériau diélectrique (13), puis le matériau de planarisation (16) est déposé dans les trous d'interconnexion et sur le matériau diélectrique, et le matériau de barrière (17) est déposé sur le matériau de planarisation. Les tranchées sont ensuite formées par lithographie dans le matériau de représentation (19), gravées à travers le matériau de barrière à l'intérieur du matériau de planarisation, et le motif de tranchées est transféré sur le matériau diélectrique. Pendant et après le déroulement de chacune de ces étapes, les matériaux de représentation, de barrière et de planarisation sont éliminés. La structure à damasquinage double obtenue peut alors être métallisée. Ce procédé permet de supprimer le problème de contamination de la photorésine par le matériau diélectrique de niveau intermédiaire.
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