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1. (WO2004104975) PIXEL CIRCUIT, DISPLAY UNIT, AND PIXEL CIRCUIT DRIVE METHOD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2004/104975 International Application No.: PCT/JP2004/007304
Publication Date: 02.12.2004 International Filing Date: 21.05.2004
IPC:
G09G 3/20 (2006.01) ,G09G 3/30 (2006.01) ,H01L 21/8234 (2006.01) ,H01L 27/06 (2006.01) ,H01L 27/088 (2006.01) ,H01L 29/786 (2006.01) ,H03K 17/687 (2006.01) ,H05B 33/14 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
22
using controlled light sources
30
using electroluminescent panels
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
51
characterised by the use of specified components
56
by the use, as active elements, of semiconductor devices
687
the devices being field-effect transistors
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
B
ELECTRIC HEATING; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR
33
Electroluminescent light sources
12
Light sources with substantially two-dimensional radiating surfaces
14
characterised by the chemical or physical composition or the arrangement of the electroluminescent material
Applicants:
ソニー株式会社 SONY CORPORATION [JP/JP]; 〒1410001 東京都品川区北品川6丁目7番35号 Tokyo 7-35, Kitashinagawa 6-chome, Shinagawa-ku, Tokyo 1410001, JP (AllExceptUS)
内野 勝秀 UCHINO, Katsuhide [JP/JP]; JP (UsOnly)
山下 淳一 YAMASHITA, Junichi [JP/JP]; JP (UsOnly)
山本 哲郎 YAMAMOTO, Tetsuro [JP/JP]; JP (UsOnly)
Inventors:
内野 勝秀 UCHINO, Katsuhide; JP
山下 淳一 YAMASHITA, Junichi; JP
山本 哲郎 YAMAMOTO, Tetsuro; JP
Agent:
佐藤 隆久 SATOH, Takahisa; 〒1110052 東京都台東区柳橋2丁目4番2号 創進国際特許事務所 Tokyo Sohshin International Patent Office, 4-2, Yanagibashi 2-chome, Taito-ku, Tokyo 1110052, JP
Priority Data:
2003-14675823.05.2003JP
Title (EN) PIXEL CIRCUIT, DISPLAY UNIT, AND PIXEL CIRCUIT DRIVE METHOD
(FR) CIRCUIT DE PIXELS, UNITE D'AFFICHAGE ET PROCEDE D'ACTIVATION D'UN CIRCUIT DE PIXELS
(JA) 画素回路、表示装置、および画素回路の駆動方法
Abstract:
(EN) A pixel circuit, a display unit and a pixel circuit drive method which enable a source follower output free from luminance deterioration even when the current-voltage characteristics of a light emitting element change with time, the source follower circuit of an n-channel transistor, and the use of an n-channel transistor as an EL drive element with the current anode/catode electrodes still used, wherein the souurce of a TFT (111) as a dirve transistor is connected to the anode of a light emitting element (114) with its drain connected to a power supply potential (VCC), a capacitor (C111) is connected between the gate and source of the TFT (111), and the source potential of the TFT (111) is connected to a fixed potential via a TFT (113) as a switch transistor.
(FR) L'invention concerne un circuit de pixels, une unité d'affichage ainsi qu'un procédé d'activation d'un circuit de pixels qui permettent d'obtenir une sortie de montage à source suiveuse présentant une luminance intacte même si les caractéristiques courant/tension d'un élément électroluminescent changent avec le temps, le montage à source suiveuse d'un transistor à canal N, et l'utilisation d'un transistor à canal N en tant qu'élément d'activation d'élément électroluminescent dont les électrodes anode/cathode sont toujours employées. Selon l'invention : la source d'un TFT (111) servant de transistor d'attaque est reliée à l'anode d'un élément électroluminescent (114), le drain étant relié à un potentiel d'alimentation (VCC) ; un condensateur (C111) est relié entre la grille et la source du TFT (111), et ; le potentiel source du TFT (111) est relié à un potentiel fixe, par l'intermédiaire d'un TFT (113) qui sert de transistor de commutation.
(JA) 発光素子の電流−電圧特性が経時変化しても、輝度劣化の無いソースフォロワー出力が行え、nチャネルトランジスタのソースフォロワー回路が可能となり、現状のアノード・カソード電極を用いたままで、nチャネルトランジスタをELの駆動素子として用いることができる画素回路、表示装置、および画素回路の駆動方法であって、駆動トランジスタとしてのTFT111のソースが発光素子114のアノードに接続され、ドレインが電源電位VCCに接続され、TFT111のゲート・ソース間にキャパシタC111が接続され、TFT111のソース電位をスイッチトランジスタとしてのTFT113に介して固定電位に接続する。
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
KR1020060023534EP1628283JP2004347993US20070057873US20120169794CN1795484
US20130321250US20130321383US20140247204US20140327665EP2996108US20170229067
US20180053468US20180254007