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1. (WO2004097836) MIRROR IMAGE MEMORY CELL TRANSISTOR PAIRS FEATURING POLY FLOATING SPACERS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2004/097836 International Application No.: PCT/US2004/010478
Publication Date: 11.11.2004 International Filing Date: 06.04.2004
Chapter 2 Demand Filed: 23.02.2005
IPC:
H01L 21/8247 (2006.01) ,H01L 27/115 (2006.01) ,H01L 29/423 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8246
Read-only memory structures (ROM)
8247
electrically-programmable (EPROM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
Applicants: ATMEL CORPORATION[US/US]; 2325 Orchard Parkway San Jose, CA 95131, US (AllExceptUS)
Inventors: LOJEK, Bohumil; US
Agent: SCHNECK, Thomas; Schneck & Schneck P.O. Box 2-E San Jose, CA 95109-0005, US
Priority Data:
10/423,63725.04.2003US
Title (EN) MIRROR IMAGE MEMORY CELL TRANSISTOR PAIRS FEATURING POLY FLOATING SPACERS
(FR) PAIRES DE TRANSISTORS DE MEMORISATION SYMETRIQUES SE CARACTERISANT PAR DES ESPACEURS POLY FLOTTANTS
Abstract:
(EN) By arranging floating spacer (27, 29) and gate (17, 19) non-volatile memory transistors in symmetric (31) pairs, increased chip density may be attained. For each pair of such transistors, the floating gates (17, 19) are laterally aligned with floating spacers (27, 29) appearing on laterally outward edges of each floating gate. At laterally inward edges, the two transistors share a common drain electrode (25). The transistors are independent of each other except for the shared drain electrode. Tunnel oxide (30) separates the floating spacer from the floating gate, but both the spacer and the gate are maintained at a common potential, thereby providing dual paths for charge exiting the tunnel oxide, as the charged is propelled by a programming voltage. The pairs of transistors can be aligned in columns (e.g., Fig. 18) with the direction of the columns orthogonal to the direction of the pairs, thereby forming a memory array.
(FR) La disposition symétrique de transistors de mémoire rémanente à grilles (17, 19) et à espaceurs flottants (27, 29) permet d'obtenir une densité de puce accrue. Pour chaque de transistors, les grilles flottantes (17, 19) sont alignées latéralement avec les espaceurs flottants (27, 29) apparaissant sur les bords latéralement extérieurs de chaque grille flottante. Au niveau des bords latéralement intérieurs, les deux transistors partagent une électrode drain commune (25). Les transistors sont indépendants les uns des autres sauf pour ce qui concerne l'électrode de drain partagée. L'oxyde tunnel (30) sépare l'espaceur flottant de la grille flottante, ces derniers étant maintenus à un potentiel commun, ce qui permet de produire des trajets doubles pour la charge sortant de l'oxyde tunnel, lorsque la charge est propulsée par une tension de programmation. Les paires de transistors peuvent être alignées en colonnes (ex.fig.18) orthogonales par rapport à la direction des paires, ce qui permet de former une matrice mémoire.
front page image
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)