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Machine translation
1. (WO2004095572) A METHOD OF FABRICATING A CMOS DEVICE WITH DUAL METAL GATE ELECTRODES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2004/095572    International Application No.:    PCT/SG2004/000100
Publication Date: 04.11.2004 International Filing Date: 19.04.2004
IPC:
H01L 21/28 (2006.01), H01L 21/8238 (2006.01), H01L 29/49 (2006.01), H01L 29/51 (2006.01)
Applicants: NATIONAL UNIVERSITY OF SINGAPORE [SG/SG]; 10 Kent Ridge Crescent, Singapore 119260 (SG) (For All Designated States Except US).
AGENCY FOR SCIENCE TECHNOLOGY AND RESEARCH [SG/SG]; 20 Biopolis Way, #07-01 Centros, Singapore 138668 (SG) (For All Designated States Except US).
PARK, Chang Seo [KR/SG]; (SG) (For US Only).
CHO, Byung Jin [KR/SG]; (SG) (For US Only).
NARAYANAN, Balasubramanian [SG/SG]; (SG) (For US Only)
Inventors: PARK, Chang Seo; (SG).
CHO, Byung Jin; (SG).
NARAYANAN, Balasubramanian; (SG)
Agent: ELLA CHEONG SPRUSON & FERGUSON (SINGAPORE) PTE LTD; P.O. Box 1531, Robinson Road Post Office, Singapore 903031 (SG)
Priority Data:
60/464,936 22.04.2003 US
Title (EN) A METHOD OF FABRICATING A CMOS DEVICE WITH DUAL METAL GATE ELECTRODES
(FR) PROCEDE DE FABRICATION DE CMOS A ELECTRODES DE GRILLE BIMETALLIQUES
Abstract: front page image
(EN)A method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AINx) buffer layer (28) between the metal gate (30) and gate dielectric (26) during processing for preventing the gate dielectric (26) from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer (28) is completely consumed through reaction with the metal gate (30) and a new metal alloy (38, 40) is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer (28) and gate metals (30) play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.
(FR)La présente invention concerne un procédé pour la construction d'une structure de CMOS à grille bimétallique au moyen d'une couche tampon (28) ultrafine de nitrure d'aluminium (AlNx) entre la grille métallique (30) et le diélectrique de grille (26) pendant le traitement, de façon à empêcher que le diélectrique de grille (26) ne soit découvert pendant l'attaque chimique du métal. Une fois que le métal sacrificiel de la grille est parti, on soumet à recuit la structure CMOS. Pendant le recuit, la réaction avec la grille de métal (30) fait disparaître complètement la couche tampon (28), et il se forme un nouvel alliage de métaux (38, 40) ne provoquant qu'un épaississement minimal de l'oxyde équivalent. La couche tampon (28) et les métaux de grille (30) jouent un rôle clé dans la détermination des fonctions de travail de l'interface métal/diélectrique car les fonctions de travail des métaux de grille d'origine se modifient au recuit.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)