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1. (WO2004034453) METHOD FOR TREATING SEMICONDUCTOR MATERIAL
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2004/034453    International Application No.:    PCT/US2003/031404
Publication Date: 22.04.2004 International Filing Date: 03.10.2003
Chapter 2 Demand Filed:    04.05.2004    
IPC:
C30B 33/00 (2006.01), H01L 21/20 (2006.01), H01L 21/302 (2006.01), H01L 21/3065 (2006.01)
Applicants: SILICON GENESIS CORPORATION [US/US]; 61 Daggett Drive, San Jose, CA 95134 (US)
Inventors: MALIK, Igor, J.; (US).
KANG, Sien, G.; (US).
FUERFANGER, Martin; (US).
KIRK, Harry; (US).
FLAT, Ariel; (US).
CURRENT, Michael, Ira; (US).
ONG, Philip, James; (US)
Agent: OGAWA, Richard, T.; Townsend and Townsend and Crew LLP, Two Embarcadero Center, 8th Floor, San Francisco, CA 94111-3834 (US)
Priority Data:
10/264,393 04.10.2002 US
60/484,181 30.06.2003 US
Title (EN) METHOD FOR TREATING SEMICONDUCTOR MATERIAL
(FR) PROCEDE DE TRAITEMENT D'UN MATERIAU SEMI-CONDUCTEUR
Abstract: front page image
(EN)The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained semiconductor layer, having a first lattice constant, on a wafer. The method further comprises etch annealing the strained semiconductor layer, wherein the strained semiconductor layer is relaxed. The methodcontrols the surface roughness of the semiconductor layers. The method also has the unexpected benefit of reducing dislocations in the semiconductor layers.
(FR)La présente invention concerne un procédé de formation d'une couche semi-conductrice contrainte. Ce procédé consiste à former une couche semi-conductrice contrainte, présentant une première constante de réseau, sur une tranche ; puis à décaper-recuire la couche semi-conductrice contrainte, laquelle couche semi-conductrice contrainte est ainsi relaxée. Ce procédé permet de modifier la rugosité de surface des couches semi-conductrices. Cette invention présente également l'avantage inattendu de réduire les dislocations dans les couches semi-conductrices.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)