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Machine translation
1. (WO2004029978) HIGHLY COMPACT NON-VOLATILE MEMORY AND METHOD THEREFOR WITH INTERNAL SERIAL BUSES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2004/029978    International Application No.:    PCT/US2003/029182
Publication Date: 08.04.2004 International Filing Date: 18.09.2003
IPC:
G11C 7/10 (2006.01), G11C 16/10 (2006.01), G11C 16/26 (2006.01)
Applicants: SANDISK CORPORATION [US/US]; 140 Caspian Court, Sunnyvale, CA 94089 (US)
Inventors: CERNEA, Raul-Adrian; (US)
Agent: YAU, Philip; PARSONS HSUE & DE RUNTZ LLP, 655 Montgomery Street, San Francisco, CA 94111 (US)
Priority Data:
10/254,919 24.09.2002 US
Title (EN) HIGHLY COMPACT NON-VOLATILE MEMORY AND METHOD THEREFOR WITH INTERNAL SERIAL BUSES
(FR) MEMOIRE NON VOLATILE TRES COMPACTE ET PROCEDE ASSOCIE FAISANT INTERVENIR DES BUS SERIE INTERNES
Abstract: front page image
(EN)A non-volatile memory device capable of reading and writing a large number of memory cells with multiple A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits among each stack are factored out. In one aspect, a serial bus allows communication between components in each stack, thereby reducing the number of connections in a stack to a minimum. A bus controller sends control and timing signals to control the operation of the components and their interactions through the serial bus. In a preferred embodiment, the bus transactions of corresponding components in all the similar stacks are controlled simultaneously.
(FR)L'invention concerne une mémoire non volatile permettant de lire/écrire des données à partir/dans un grand nombre de cellules de mémoire avec plusieurs circuits de lecture/écriture en parallèle, comprenant une architecture qui réduit la redondance dans ces circuits de lecture/écriture au minimum. Ces circuits de lecture/écriture sont organisés en une banque de piles de composants similaires. Les circuits redondants de chaque pile sont factorisés. Dans un aspect, un bus série permet aux composants de chaque pile de communiquer entre eux, réduisant ainsi le nombre de connexions dans une pile au minimum. Un contrôleur de bus transmet des signaux de commande et de synchronisation pour commander le fonctionnement des composants et leurs interactions par le bus série. Dans un mode de réalisation préféré, les échanges par bus de composants correspondants dans toutes les piles similaires sont commandés simultanément.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)