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Machine translation
1. (WO2004027602) SYSTEM AND METHOD FOR A FULLY SYNTHESIZABLE SUPERPIPELINED VLIW PROCESSOR
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2004/027602    International Application No.:    PCT/US2003/029705
Publication Date: 01.04.2004 International Filing Date: 17.09.2003
IPC:
G06F 9/30 (2006.01), G06F 9/38 (2006.01)
Applicants: KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1, NL-5621 BA Eindhoven (NL) (For All Designated States Except US).
SLAVENBURG, Gerrit [US/US]; (US) (For US Only).
VAN DE WAERDT, Jan-Willem [US/US]; (US) (For US Only)
Inventors: SLAVENBURG, Gerrit; (US).
VAN DE WAERDT, Jan-Willem; (US)
Common
Representative:
KONINKLIJKE PHILIPS ELECTRONICS N.V.; c/o LESTER, Shannon, 1109 McKay Drive, M/S-41SJ, San Jose, CA 95131 (US)
Priority Data:
60/411,589 17.09.2002 US
60/468,931 07.05.2003 US
Title (EN) SYSTEM AND METHOD FOR A FULLY SYNTHESIZABLE SUPERPIPELINED VLIW PROCESSOR
(FR) SYSTEME ET PROCEDE POUR PROCESSEUR VLIW SUPER-PIPELINE ENTIEREMENT SYNTHETISABLE
Abstract: front page image
(EN)The invention relates to a method to create a fully synthesizable super-pipelined VLIW processor that creates both a high frequency operating processor as well as a high performance processor. It is proposed to split the operation units of the VLIW into two subsets. The first subset unit executes a basic loop with only a single register delay in the loop as the other unit, although connected around the first unit, has the conventional delay in the loop.
(FR)Cette invention se rapporte à un procédé servant à créer un processeur VLIW super-pipeline entièrement synthétisable, ce procédé créant ainsi à la fois un processeur fonctionnant à hautes fréquences et un processeur haute performance. On propose de diviser les unités d'exploitation du processeur VLIW en deux sous-ensembles. Le premier sous-ensemble exécute une boucle de base avec un seul le retard de registre dans la boucle, alors que l'autre sous-ensemble, bien que connecté autour du premier sous-ensemble, agit dans la boucle avec un retard traditionnel.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NI, NO, NZ, OM, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)