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1. WO2004025457 - PREFETCHING DATA IN COMPUTER SYSTEM

Publication Number WO/2004/025457
Publication Date 25.03.2004
International Application No. PCT/US2003/027716
International Filing Date 06.09.2003
Chapter 2 Demand Filed 26.03.2004
IPC
G06F 9/00 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
G06F 9/38 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
G06F 12/00 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
CPC
G06F 12/0862
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0862with prefetch
G06F 12/0897
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0893Caches characterised by their organisation or structure
0897with two or more cache hierarchy levels
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • SPRANGLE, Eric
  • ROHILLAH, Anwar
Agents
  • MALLIE, Michael J.
Priority Data
10/244,25016.09.2002US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PREFETCHING DATA IN COMPUTER SYSTEM
(FR) LECTURE ANTICIPEE DE DONNEES DANS UN SYSTEME INFORMATIQUE
Abstract
(EN)
A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.
(FR)
La présente invention se rapporte à un procédé et à un appareil permettant de détecter et de filtrer des lignes d'antémémoire redondantes dans une file d'attente en entrée de lecture anticipée, et d'ajuster dynamiquement la taille de fenêtre d'un détecteur en fonction du nombre d'entrées du détecteur dans la file d'attente pour le bus de commande antémémoire-à-mémoire. Les détecteurs correspondent à des adresses de lignes de l'antémémoire qui peuvent représenter des recherches infructueuses dans l'antémémoire à divers niveaux de l'antémémoire.
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