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1. (WO2004017399) MICROELECTRONIC PACKAGES WITH SELF-ALIGNING FEATURES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2004/017399 International Application No.: PCT/US2003/025256
Publication Date: 26.02.2004 International Filing Date: 13.08.2003
IPC:
H01L 23/498 (2006.01) ,H01L 23/544 (2006.01) ,H01L 25/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
544
Marks applied to semiconductor devices, e.g. registration marks, test patterns
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
10
the devices having separate containers
Applicants:
TESSERA, INC. [US/US]; 3099 Orchard Drive San Jose, CA 95134, US
Inventors:
BANG, Kyong-Mo; US
KANG, Teck-Gyu; US
PARK, Jae, M.; US
Agent:
GARNER, Steven, A.; Lerner, David, Littenberg, Krumholz & Mentlik, LLP 600 South Avenue West Westfield, NJ 07090, US
Priority Data:
60/403,93916.08.2002US
Title (EN) MICROELECTRONIC PACKAGES WITH SELF-ALIGNING FEATURES
(FR) BOITIERS MICROELECTRONIQUES A ALIGNEMENT AUTOMATIQUE
Abstract:
(EN) A microelectronic package is made by a process which includes folding a substrate (20). Alignment elements (54, 58) on different parts of the substrate (20) engage one another during the folding process to position the parts of the substrate (20) precisely relative to one another. One or more of the alignment elements (54, 58) may be a mass of an overmolding encapsulant covering a chip.
(FR) L'invention concerne un boîtier microélectronique fabriqué selon un procédé consistant à plier un substrat (20). Des éléments d'alignement (54, 58) situés sur différentes parties de ce substrat (20) s'engagent l'un sur l'autre lors du processus de pliage de façon à permettre un positionnement précis des parties dudit substrat (20) l'une par rapport à l'autre. Un ou plusieurs de ces éléments d'alignement (54, 58) peuvent être constitués d'une masse d'un agent d'encapsulation par surmoulage recouvrant une puce.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NI, NO, NZ, OM, PG, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)