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Machine translation
1. (WO2004004015) SOI FIELD EFFECT TRANSISTOR ELEMENT HAVING A RECOMBINATION REGION AND METHOD OF FORMING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2004/004015    International Application No.:    PCT/US2003/020791
Publication Date: 08.01.2004 International Filing Date: 24.06.2003
Chapter 2 Demand Filed:    16.12.2003    
IPC:
H01L 21/336 (2006.01), H01L 29/786 (2006.01)
Applicants: ADVANCED MICRO DEVICES, INC. [US/US]; One AMD Place, Mail Stop 68, P.O. Box 3453, Sunnyvale, CA 94088-3453 (US)
Inventors: WIECZOREK, Karsten; (DE).
HORSTMANN, Manfred; (DE).
KRUEGER, Christian; (DE)
Agent: DRAKE, Paul, S.; Advanced Micro Devices, Inc., 5204 East Ben White Boulevard, M/S 562, Austin, TX 78741 (US).
PFAU, Anton; Grünecker, Kinkeldey, Stockmair & Schwanhäusser, Anwaltssozietät, Maximilanstrasse 58, 80538 München (DE)
Priority Data:
102 29 003.3 28.06.2002 DE
10/391,255 18.03.2003 US
Title (EN) SOI FIELD EFFECT TRANSISTOR ELEMENT HAVING A RECOMBINATION REGION AND METHOD OF FORMING SAME
(FR) ELEMENT TRANSISTOR A EFFET DE CHAMP SOI DOTE D'UNE ZONE DE RECOMBINAISON ET PROCEDE DE FABRICATION ASSOCIE
Abstract: front page image
(EN)An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer 320 is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.
(FR)L'invention concerne un élément transistor silicium sur isolant (SOI) et un procédé de fabrication associé. Selon ce procédé, une concentration élevée de défauts ponctuels stationnaires est créée par inclusion, dans la zone transistor active, d'une zone présentant un léger décalage de grille. Dans un mode de réalisation, une couche de silicium germanium 320 est appliquée dans la zone active dotée d'une concentration élevée de défauts ponctuels par relâchement de la tension de la couche de silicium germanium en chauffant l'élément transistor. Les défauts ponctuels provoquent un accroissement sensible du taux de recombinaison, réduisant ainsi le nombre de supports chargés dans la zone active.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, OM, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)