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1. (WO2004003926) LOW-COST, SERIALLY-CONNECTED, MULTI-LEVEL MASK-PROGRAMMABLE READ-ONLY MEMORY
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2004/003926    International Application No.:    PCT/US2003/020051
Publication Date: 08.01.2004 International Filing Date: 25.06.2003
Chapter 2 Demand Filed:    26.01.2004    
IPC:
G11C 11/56 (2006.01), G11C 17/12 (2006.01)
Applicants: MATRIX SEMICONDUCTOR, INC. [US/US]; 3230 Scott Boulevard, Santa Clara, CA 95054 (US)
Inventors: JOHNSON, Mark, G.; (US)
Agent: GRAHAM, Andrew, C.; Zagorin, O'Brien & Graham, L.L.P., 7600B N. Capital of Texas Hwy, Suite 350, Austin, TX 78731-1191 (US).
DAVID Meldrum; D Young & Co, 21 New Fetter Lane, London EC4A 1DA (GB)
Priority Data:
10/185,208 27.06.2002 US
Title (EN) LOW-COST, SERIALLY-CONNECTED, MULTI-LEVEL MASK-PROGRAMMABLE READ-ONLY MEMORY
(FR) MEMOIRE ROM PROGRAMMABLE PAR MASQUE MULTINIVEAU, RELIEE EN SERIE, DE FAIBLE COUT
Abstract: front page image
(EN)An integrated circuit includes a serially-connected, multi-level, mask-programmed read-only memory array. The memory cells are preferably programmed using selective ion implantation of at least two threshold-adjusting ion implants during the manufacture of the integrated circuit to store more than one bit of information within each memory cell, which are chosen to generate an evenly spaced set of different transistor threshold voltages.
(FR)L'invention concerne un circuit intégré comprenant un agencement de mémoire ROM programmée par masque, multiniveau et connectée en série. Les cellules de mémoire sont de préférence programmées au moyen d'une implantation ionique sélective d'au moins deux implants ioniques de réglage de seuil, lors de la fabrication du circuit intégré, pour stocker au moins un bit d'information à l'intérieur de chaque cellule de mémoire, lesquels implants étant choisis pour générer un ensemble régulièrement espacé de tensions seuils de différents transistors.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NI, NO, NZ, OM, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, RO, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)