A flash memory (1) produced by the multi-value storage technique for storing information of two or more bits comprises four banks (2a to 2d). For example, on the left-hand side of a bank (2a), a data latch (6a) is disposed along one short side of the bank (2a), while on the right-hand side, a data latch (6b) is disposed along the other short side. Under the data latches (6a, 6b) in the drawing, arithmetic circuits (7a, 7b) are disposed, respectively. Each of the data latches (6a, 6b) is composed of an SRAM. A sense latch (5a) is divided into two left and right halves with respect to the center of the sense latch array. The divided sense latch (5a) is connected to the data latches (6a, 6b) through signal lines wired along both short sides of the bank (2a).