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1. (WO2003063167) SYSTEM AND METHOD FOR PROGRAMMING ONO DUAL BIT MEMORY CELLS

Pub. No.:    WO/2003/063167    International Application No.:    PCT/US2002/040775
Publication Date: Jul 31, 2003 International Filing Date: Dec 17, 2002
IPC: G11C 11/56
G11C 16/04
G11C 16/10
G11C 16/34
Applicants: ADVANCED MICRO DEVICES, INC.
Inventors: HAMILTON, Darlene
THURGATE, Timothy
WANG, Janet, S. Y.
HAN, Michael, K.
DERHACOBIAN, Narbeh
Title: SYSTEM AND METHOD FOR PROGRAMMING ONO DUAL BIT MEMORY CELLS
Abstract:
A system and methodology is provided for programming first bit (CO, C2, C4, C6) and second bit (C1, C3, C5, C7) of a memory array (68) of dual bit memory cells (10, 82, 84, 86, 88) at a substantially high delta VT. The substantially higher VT assures that the memory array (68) will maintain programmed data and erase data consistently after higher temperature stresses and/or custumer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit (C0, C2, C4, C6) of the memory cell (10, 82, 84, 86, 88) causes the second bit (C1, C3, C5, C7) to program harder and faster due to the shorter channel (8) length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) that assures a controlled first bit VT and slows down programming of the second bit (C1,C3, C5, C7). Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.