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1. (WO2003061006) STACKED DIE IN DIE BGA PACKAGE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2003/061006 International Application No.: PCT/US2003/000569
Publication Date: 24.07.2003 International Filing Date: 09.01.2003
Chapter 2 Demand Filed: 16.07.2003
IPC:
H01L 23/31 (2006.01) ,H01L 23/498 (2006.01) ,H01L 25/065 (2006.01) ,H01L 29/06 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Applicants:
MICRON TECHNOLOGY, INC [US/US]; 8000 S.Federal Way Boise, ID 83706-9632, US
Inventors:
TAN, Hock Chuan; SG
LIM, Thiam Chye; SG
TAN, Victor Cher Khng; SG
NEO, Chee peng; SG
TAN, Michael, Kian, Shing; SG
CHEW, Beng Chye; SG
POUR, Cheng, poh; SG
Agent:
STRODTHOFF, Kristine, M. ; Whyte Herscgieck Didek S. C. 111 E. Wisconsin Avenue, Suite 2100 Milwaukee, WI 53202, US
Priority Data:
10/068,15905.02.2002US
200200134-509.01.2002SG
Title (EN) STACKED DIE IN DIE BGA PACKAGE
(FR) PUCES SUPERPOSEES DISPOSEES DANS UN BOITIER BGA
Abstract:
(EN) Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.
(FR) L'invention concerne des dispositifs à semi-conducteurs et des ensembles de puces superposées, ainsi que des procédés de fabrication de ces dispositifs et ensembles permettant d'améliorer la densité des dispositifs à semi-conducteurs.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, OM, PH, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HU, IE, IT, LU, MC, NL, PT, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20030207515US20030148597US20060292743US20080096316US20080032449US20080136045
AU2003207484