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1. (WO2003060960) HIGH DENSITY AREA ARRAY SOLDER MICROJOINING INTERCONNECT STRUCTURE AND FABRICATION METHOD
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2003/060960 International Application No.: PCT/EP2002/014911
Publication Date: 24.07.2003 International Filing Date: 19.12.2002
Chapter 2 Demand Filed: 04.07.2003
IPC:
H01L 21/00 (2006.01) ,H01L 23/485 (2006.01) ,H01L 23/498 (2006.01) ,H05K 1/03 (2006.01) ,H05K 1/11 (2006.01) ,H05K 3/34 (2006.01) ,H05K 3/38 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482
consisting of lead-in layers inseparably applied to the semiconductor body
485
consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
03
Use of materials for the substrate
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
11
Printed elements for providing electric connections to or between printed circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
30
Assembling printed circuits with electric components, e.g. with resistor
32
electrically connecting electric components or wires to printed circuits
34
by soldering
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
38
Improvement of the adhesion between the insulating substrate and the metal
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, NJ 10504, US (AE, AG, AL, AM, AT, AU, AZ, BA, BB, BE, BF, BG, BJ, BR, BY, BZ, CA, CF, CG, CH, CI, CM, CN, CO, CR, CU, CY, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GW, HR, HU, ID, IE, IL, IN, IS, IT, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, ML, MN, MR, MW, MX, MZ, NE, NL, NO, NZ, OM, PH, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, SN, SZ, TD, TG, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZM, ZW)
COMPAGNIE IBM FRANCE [FR/FR]; Tour Descartes, La Défense 5 2, Avenue Gambetta F-9400 Courbevoie, FR (MC)
Inventors:
MAGERLEIN, John, Harold; US
PETRARCA, Kevin, Shawn; US
PURUSHOTHAMAN, Sampath; US
SAMBUCETTI, Carlos, Juan; US
VOLANT, Richard, Paul; US
WALKER, George, Frederick; US
Agent:
KLEIN, Daniel; Compagnie IBM France Direction de la Propriété Intellectuelle F-06610 La Gaude, FR
Priority Data:
10/052,62018.01.2002US
Title (EN) HIGH DENSITY AREA ARRAY SOLDER MICROJOINING INTERCONNECT STRUCTURE AND FABRICATION METHOD
(FR) RESEAU HAUTE DENSITE DE STRUCTURES D'INTERCONNEXION PAR MICROJOINTS A BRASURE TENDRE ET PROCEDE DE FABRICATION
Abstract:
(EN) A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
(FR) La présente invention concerne un système permettant d'interconnecter un ensemble de microcircuits de dispositifs au moyen d'un réseau de microjoints disposés sur un support d'interconnexion. Ce support est pourvu d'un réseau dense de réceptacles de microjoints comportant une couche d'adhésion, une couche barrière et une couche de métal noble. Les tranches des dispositifs comprennent également un réseau de pastilles de microjointure comprenant une couche d'adhésion, une couche barrière et une couche de soudure fusible, les pastilles étant disposées au niveau des emplacements correspondants par rapport aux réceptacles barrières. Ces microcircuits de dispositifs sont rattachés au support au moyen des réseaux de microjoints qui constituent des interconnexions permettant d'obtenir une densité entrée/sortie très élevée ainsi qu'une densité de câblage inter-puces très élevée.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, OM, PH, PL, PT, RO, RU, SD, SE, SG, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, SI, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP1470581JP2005515628JP4012513CN1608316CA2472750AU2002363902