An insertion sorter circuit (200) and method are provided which are particularly useful for sorting channel response values of a communication signal. The sorter circuit includes a series of sorter elements (1501-150N) which each have a register (1011-101N). The circuit is configured to cascade values downwardly when one register receives a greater value than it has stored (1021-102N), which value is not greater than the value stored in any upstream register. At the end of processing the values, the most significant values are stored in the registers (1011-101N), the sum (105) of which are the channel power estimate. The channel noise (106) variance is obtainable by applying a system dependent scaling factor to the sum (105) of the least significant values processed.