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1. WO2003038896 - BALL GRID ARRAY WITH X-RAY ALIGNMENT MARK

Publication Number WO/2003/038896
Publication Date 08.05.2003
International Application No. PCT/US2002/034809
International Filing Date 29.10.2002
Chapter 2 Demand Filed 31.05.2003
IPC
H01L 21/60 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/498 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488consisting of soldered or bonded constructions
498Leads on insulating substrates
H01L 23/544 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
544Marks applied to semiconductor devices, e.g. registration marks, test patterns
H05K 1/02 2006.1
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1Printed circuits
02Details
H05K 3/30 2006.1
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
30Assembling printed circuits with electric components, e.g. with resistor
CPC
H01L 2223/54406
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2223Details relating to semiconductor or other solid state devices covered by the group H01L23/00
544Marks applied to semiconductor devices or parts
54406comprising alphanumeric information
H01L 2223/5442
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2223Details relating to semiconductor or other solid state devices covered by the group H01L23/00
544Marks applied to semiconductor devices or parts
5442comprising non digital, non alphanumeric information, e.g. symbols
H01L 2223/54473
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2223Details relating to semiconductor or other solid state devices covered by the group H01L23/00
544Marks applied to semiconductor devices or parts
54473for use after dicing
H01L 2223/5448
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2223Details relating to semiconductor or other solid state devices covered by the group H01L23/00
544Marks applied to semiconductor devices or parts
54473for use after dicing
5448Located on chip prior to dicing and remaining on chip after dicing
H01L 2224/05568
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
0556Disposition
05568the whole external layer protruding from the surface
H01L 2224/05573
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05573Single external layer
Applicants
  • QUALCOMM, INCORPORATED [US]/[US]
Inventors
  • PRIMROSE, Paul W.
Agents
  • WADSWORTH, Philip R.
Priority Data
10/016,28830.10.2001US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) BALL GRID ARRAY WITH X-RAY ALIGNMENT MARK
(FR) MARQUEUR VISIBLE AUX RAYONS X DE L'ORIENTATION DE GRILLES MATRICIELLES A BILLES
Abstract
(EN) An apparatus and method for inspecting electronic component orientation along with x-ray verification of connection integrity is presented. An exemplary method comprises providing an electronic component 100 for surface mount integration and providing an x-ray visible orientation indicator 300, 402, 500, 600 for the electronic component 100 such that proper orientation of the electronic component 100 is verifiable by x-ray inspection after performing surface mount integration of the electronic component. The x-ray inspection also makes connection integrity of the electronic component 100 verifiable.
(FR) L'invention porte sur un appareil et un procédé d'examen de l'orientation de composants électroniques et de vérification de l'intégrité de leurs connexions. Le procédé donné en exemple utilise un composant électronique (100) monté en surface et un indicateur d'orientation (300, 402, 500, 600) du composant électronique (100) visible aux rayons X permettant de vérifier aux rayons X l'orientation correcte du composant électronique (100) après son montage en surface ainsi que l'intégrité de ses connexions.
Related patent documents
BRPI0206243This application is not viewable in PATENTSCOPE because the national phase entry has not been published yet or the national entry is issued from a country that does not share data with WIPO or there is a formatting issue or an unavailability of the application.
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