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1. WO2003036650 - METHOD FOR ERASING A MEMORY CELL

Publication Number WO/2003/036650
Publication Date 01.05.2003
International Application No. PCT/IL2002/000855
International Filing Date 24.10.2002
IPC
G11C 16/14 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
14Circuits for erasing electrically, e.g. erase voltage switching circuits
CPC
G11C 16/14
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
14Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/3445
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3436Arrangements for verifying correct programming or erasure
344Arrangements for verifying correct erasure or for detecting overerased cells
3445Circuits or methods to verify correct erasure of nonvolatile memory cells
Applicants
  • SAIFUN SEMICONDUCTORS LTD. [IL]/[IL] (AllExceptUS)
  • SOFER, Yair [IL]/[IL] (UsOnly)
  • EITAN, Boaz [IL]/[IL] (UsOnly)
Inventors
  • SOFER, Yair
  • EITAN, Boaz
Agents
  • Pearl, Zeev
Priority Data
09/983,51024.10.2001US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR ERASING A MEMORY CELL
(FR) PROCEDE POUR EFFACER UNE CELLULE MEMOIRE
Abstract
(EN) A method for erasing a non-volatile memory cell array, the method including applying an erase pulse (100) to at least one bit of at least one memory cell of the array, erase verifying (102) the at least one bit with a first erase verify level, and if the bit has passed the first erase verify level, applying at least one more erase pulse (104) to the at least one bit.
(FR) La présente invention concerne un procédé pour effacer un ensemble de cellules mémoire non volatiles. Ce procédé consiste à appliquer une impulsion d'effacement sur au moins un bit d'au moins une cellule mémoire de l'ensemble, à vérifier l'effacement dudit bit avec un premier niveau de vérification d'effacement, puis, si le bit a passé ledit premier niveau de vérification d'effacement, à appliquer une autre impulsion d'effacement sur ledit bit.
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