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1. (WO2003019654) STACKED CHIP ASSEMBLY WITH STIFFENING LAYER
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2003/019654 International Application No.: PCT/US2002/026805
Publication Date: 06.03.2003 International Filing Date: 22.08.2002
IPC:
H01L 21/56 (2006.01) ,H01L 23/16 (2006.01) ,H01L 23/31 (2006.01) ,H01L 23/498 (2006.01) ,H01L 25/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
16
Fillings or auxiliary members in containers, e.g. centering rings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
10
the devices having separate containers
Applicants:
MOHAMMED, Ilyas [IN/US]; US (UsOnly)
TESSERA, INC. [US/US]; 3099 Orchard Drive San Jose, CA 95134, US (AllExceptUS)
Inventors:
MOHAMMED, Ilyas; US
Agent:
DOHERTY, Michael, J. ; Lerner, David, Littenberg, Krumholz & Mentlik, LLP 600 South Avenue West Westfield, NJ 07090, US
Priority Data:
60/314,04222.08.2001US
Title (EN) STACKED CHIP ASSEMBLY WITH STIFFENING LAYER
(FR) ENSEMBLE SUPERPOSE A PUCE COMPRENANT UNE COUCHE DE RENFORT
Abstract:
(EN) A microelectronic subassembly 210 includes a substrate 215 having a top surface 216 and at least one peripheral region 219, a microelectronic element 201 mounted over the substrate 215, a plurality of leads 218, 222 electrically connected to the microelectronic element 201 having outer ends overlying the at least one peripheral region 219 of the substrate 215, and vertical conductors 208 electrically connected with the outer ends of the leads. The subassembly includes an encapsulant layer 204 provided over the top surface 216 of the substrate 215 and around the microelectronic element 201 and the vertical conductors 208 for stiffening the substrate 215 at the at least one peripheral region 219 of the substrate for facilitating handling and testing of the subassembly.
(FR) L'invention concerne un sous-ensemble microélectronique (210) comprenant un substrat (215) avec une surface supérieure (216) et au moins une région périphérique (219), un élément microélectronique (201) monté sur le substrat (215), une pluralité de fils (218, 222) électriquement connectés à l'élément microélectronique (201) et dont les extrémités extérieures recouvrent la région périphérique (219) du substrat (215), et des conducteurs verticaux (208) électriquement connectés aux extrémités extérieures des fils. Le sous-ensemble comprend une couche (204) d'encapsulation sur la surface supérieure (216) du substrat (215) et autour de l'élément microélectronique (201) et des conducteurs verticaux (208) pour renforcer le substrat (215) au niveau de la région périphérique (219) du substrat afin de faciliter la manipulation et l'essai du sous-ensemble.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, OM, PH, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, YU, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, SK, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)