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1. (WO2003003595) RECEIVER
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2003/003595 International Application No.: PCT/JP2002/006269
Publication Date: 09.01.2003 International Filing Date: 24.06.2002
Chapter 2 Demand Filed: 22.01.2003
IPC:
H04B 1/28 (2006.01) ,H04B 1/30 (2006.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
B
TRANSMISSION
1
Details of transmission systems, not covered by a single one of groups H04B3/-H04B13/123; Details of transmission systems not characterised by the medium used for transmission
06
Receivers
16
Circuits
26
for superheterodyne receivers
28
the receiver comprising at least one semiconductor device having three or more electrodes
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
B
TRANSMISSION
1
Details of transmission systems, not covered by a single one of groups H04B3/-H04B13/123; Details of transmission systems not characterised by the medium used for transmission
06
Receivers
16
Circuits
30
for homodyne or synchrodyne receivers
Applicants: MIYAGI, Hiroshi[JP/JP]; JP (UsOnly)
NIIGATA SEIMITSU CO., LTD.[JP/JP]; 5-13, Nishishiromachi 2-chome Jouetsu-shi, Niigata 943-0834, JP (AllExceptUS)
Inventors: MIYAGI, Hiroshi; JP
Agent: AMAGAI, Masahiko; Amagai Tokkyo Jimusyo, 2nd Floor Kitashinjuku OC Build. 8-15, Kitashinjuku 1-chome Shinjuku-ku, Tokyo 169-0074, JP
Priority Data:
2001-19821329.06.2001JP
Title (EN) RECEIVER
(FR) RECEPTEUR
Abstract:
(EN) A receiver capable of reducing a low−frequency noise generated when a component is integrally formed on a semiconductor substrate by using CMOS process or MOS process. A high−frequency amplifier circuit (11), a mixing circuit (12), a local oscillator (13), intermediate−frequency filters (14, 16), an intermediate−frequency amplifier (15), a limit circuit (17), an FM detection circuit (18), and a stereo decoding circuit (19) constituting an FM receiver are formed as a single−chip part (10). This single−chip part (10) is formed on a semiconductor substrate by using the CMOS process or the MOS process. The amplification elements contained in the mixing circuit (12), the intermediate−frequency filters (14, 16), the intermediate−frequency amplifier circuit (15), and the local oscillator (13) are formed by using the p−channel type FET.
(FR) L'invention porte sur un récepteur réduisant le bruit à base fréquence apparaissant dans des composants intégrés sur substrat de semi-conducteur obtenus par procédé CMOC ou MOS. Ledit récepteur comporte: un circuit d'amplification des HF (11), un circuit de mixage (12), un oscillateur local (13), des filtres de fréquence intermédiaire (14, 16), un amplificateur des fréquence intermédiaire (15), un circuit limiteur (17), un circuit de détection de FM (18), et un circuit de décodage stéréo (19). L'ensemble constitue une puce (10) monolithique formée sur un substrat semi-conducteur par procédé CMOC ou MOS. Les éléments d'amplification du circuit de mixage (12), les filtres de fréquence intermédiaire (14, 16), l'amplificateur des fréquence intermédiaire (15), et l'oscillateur local (13) sont des FET à canal p.
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Designated States: CN, JP, KR, US
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)