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Machine translation
1. (WO2003003582) LOW POWER OPERATION MECHANISM AND METHOD
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2003/003582    International Application No.:    PCT/US2002/008088
Publication Date: 09.01.2003 International Filing Date: 14.03.2002
Chapter 2 Demand Filed:    14.01.2003    
IPC:
H01L 29/10 (2006.01), H01L 29/78 (2006.01), H03K 19/00 (2006.01)
Applicants: INTEL CORPORATION [US/US]; 2200 Mission College Boulevard, Santa Clara, CA 95052 (US)
Inventors: RAVICHANDRAN, Krishnan; (US).
BARANY, Micah; (US).
JACKSON, Robert; (US).
ZHANG, Kevin; (US)
Agent: BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP; c/o Grace Abercrombie, 1279 Oakmead Parkway, Sunnyvale, CA 94086 (US)
Priority Data:
09/892,632 28.06.2001 US
Title (EN) LOW POWER OPERATION MECHANISM AND METHOD
(FR) MECANISME DE FONCTIONNEMENT A BASSE PUISSANCE, ET PROCEDE
Abstract: front page image
(EN)An apparatus and method are provided for powering a chip having at least one transistor. A voltage regulating device (110) may apply a first voltage and a second voltage to the transistor. The voltage regulating device may include a mechanism (120) to apply a third voltage to a body contact of the transistor while applying the first voltage to the transistor. This places the transistor in a reverse body bias mode which conserves energy by reducing leakage current.
(FR)L'invention concerne un dispositif et un procédé permettant d'alimenter une puce qui comprend au moins un transistor. Il est possible d'appliquer des première et seconde tensions au transistor, par le biais d'un régulateur de tension. Le régulateur peut comprendre un mécanisme qui permet d'appliquer une troisième tension à un contact du substrat du transistor, tout en appliquant la première tension au transistor, lequel est alors en mode de polarisation inverse du substrat, c'est-à-dire en mode de conservation d'énergie grâce à la réduction des courants de fuite.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, OM, PH, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)