WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2003003463) ACTIVE MATRIX OF THIN-FILM TRANSISTORS (TFT) FOR AN OPTICAL SENSOR OR DISPLAY SCREEN
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2003/003463    International Application No.:    PCT/FR2002/002258
Publication Date: 09.01.2003 International Filing Date: 28.06.2002
Chapter 2 Demand Filed:    28.01.2003    
IPC:
G02F 1/1362 (2006.01)
Applicants: THALES AVIONICS LCD S.A. [FR/FR]; 173, boulevard Haussmann, F-75008 Paris (FR) (For All Designated States Except US).
LEBRUN, Hugues [FR/FR]; (FR) (For US Only)
Inventors: LEBRUN, Hugues; (FR)
Agent: NGUYEN, Christian; Thales Intellectual Property, 31-33 Avenue Aristide Briand, F-94117 Arcueil Cedex (FR)
Priority Data:
01/08625 29.06.2001 FR
Title (EN) ACTIVE MATRIX OF THIN-FILM TRANSISTORS (TFT) FOR AN OPTICAL SENSOR OR DISPLAY SCREEN
(FR) MATRICE ACTIVE DE TRANSISTORS EN COUCHES MINCES OU TFT POUR CAPTEUR OPTIQUE OU ECRAN DE VISUALISATION
Abstract: front page image
(EN)The invention relates to an active matrix of thin-film transistors or TFTs for an optical sensor consisting of: a matrix of transistors formed on a substrate, each transistor comprising a gate, a drain (8) and a source (9); a set of lines and columns connected respectively to the gates and to a transistor electrode; pixel electrodes; and, according to the invention, a set of capacitive electrodes (14) which are disposed at the same level as the transistor electrodes so as to form storage capacities with the pixel electrodes.
(FR)L'invention concerne une matrice active de transistors en couches minces ou TFT pour capteur optique comprenant une matrice de transistors formée sur un substrat comportant une grille, un drain (8) et une source (9), un ensemble de lignes et de colonnes connectées respectivement aux grilles et à une électrode du transistor, des électrodes de pixel et selon l'invention une ensemble d'électrodes capacitives (14) situées au même niveau que les électrodes des transistors de manière à former avec les électrodes de pixel des capacités de stockage.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, OM, PH, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: French (FR)
Filing Language: French (FR)