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1. (WO2003003436) SIDEWALL SPACER DEFINITION OF GATES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2003/003436 International Application No.: PCT/US2002/002994
Publication Date: 09.01.2003 International Filing Date: 31.01.2002
Chapter 2 Demand Filed: 17.01.2003
IPC:
H01L 21/28 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
Applicants: ADVANCED MICRO DEVICES, INC.[US/US]; One AMD Place, Mail Stop 68 P.O. Box 3453 Sunnyvale, CA 94088-3453, US
Inventors: LUKANC, Todd, P.; US
LYONS, Christopher, F.; US
Agent: RODDY, Richard, J.; Advance Micro Devices, Inc. One AMD Place Mail Stop 68 Sunnyvale, CA 94088-3453, US
PICKER, Madeline M; Brookes Batchellor 102-108 Clerkenwell Road London EC1M 5SA, GB
Priority Data:
09/891,30627.06.2001US
Title (EN) SIDEWALL SPACER DEFINITION OF GATES
(FR) DEFINITION DE SEPARATEUR DE FLANCS DE GRILLES
Abstract:
(EN) A method of forming features on a semiconductor device uses sidewall spacers, and includes providing a sidewall template (210) having first (224) and second (228) sidewall regions. A spacer layer (212) of a spacer material is formed over the sidewall template (210). The spacer layer (212) is then etched in a first etch to remove a first region (222) of the spacer layer over the first sidewall region (224) while leaving a second region (226) of the spacer layer (212) over the second sidewall region (228). The spacer layer (212) is again etched in a second etch to for at least one sidewall spacer (234).
(FR) La présente invention concerne un procédé de formation d'éléments sur un dispositif semi-conducteur utilisant des séparateurs de flancs, et comportant la réalisation d'un gabarit de flanc (210) comprenant des première (224) et deuxième régions de flancs. Une couche de séparation (212) d'un matériau de séparation est formée sur le gabarit de flanc (210). La couche de séparation (212) est ensuite gravée dans une première opération de gravure pour enlever une première région (22) de la couche de séparation sur la région du premier flanc (224) en laissant subsister une deuxième région (226) de la couche de séparation (212) sur la deuxième région de flanc (228). La couche de séparation (212) est gravée une nouvelle fois dans une deuxième opération de gravure pour au moins un séparateur de flanc (234)
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PH, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)