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1. WO2003003379 - NON-VOLATILE MEMORY AND ACCELERATED TEST METHOD FOR ADDRESS DECODER BY ADDED MODIFIED DUMMY MEMORY CELLS

Publication Number WO/2003/003379
Publication Date 09.01.2003
International Application No. PCT/IB2002/002489
International Filing Date 28.06.2002
IPC
G11C 29/02 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/24 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
04Detection or location of defective memory elements
08Functional testing, e.g. testing during refresh, power-on self testing or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing
18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
24Accessing extra cells, e.g. dummy cells or redundant cells
CPC
G11C 16/08
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
08Address circuits; Decoders; Word-line control circuits
G11C 29/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/24
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
24Accessing extra cells, e.g. dummy cells or redundant cells
Applicants
  • KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL]/[NL] (AllExceptUS)
  • GAPPISCH, Steffen [DE]/[NL] (UsOnly)
  • FARKAS, Georg [CH]/[NL] (UsOnly)
Inventors
  • GAPPISCH, Steffen
  • FARKAS, Georg
Agents
  • VOLMER, Georg
Priority Data
01115963.929.06.2001EP
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) NON-VOLATILE MEMORY AND ACCELERATED TEST METHOD FOR ADDRESS DECODER BY ADDED MODIFIED DUMMY MEMORY CELLS
(FR) MEMOIRE NON VOLATILE ET PROCEDE D'ESSAI ACCELERE POUR DECODEUR D'ADRESSE PAR CELLULES DE MEMOIRE DE COMPENSATION MODIFIEES
Abstract
(EN) This invention relates to the structure and design of a non-volatile memory, in particular to such memories embedded or integrated into integrated circuits (ICs). To solve the problem of excessive test times for such memories, especially the testing of the associated decoders, a modification of a predetermined, memory-size-dependant number of nonvolatile memory cells turns them into ROM cells with a fixed content pattern. Since these additional ROM cells are just modified non-volatile cells, they differ only slightly from the latter. Thus, they do not require much effort during manufacturing and, even more important, use only small additional space on the memory chip or the integrated circuit, but provide significant advantage for the testing. When using pairs of essentially symmetrical non-volatile memory cells, each pair having a common bit line, the removal or interruption of this bitline contact may serve to impress a fixed value, e.g. a '0', into this pair and vice versa. During test, a simple and therefore only minimal time requiring pattern, preferably a checkerboard pattern, is written into and read from the non-volatile memory, allowing a quick determination of the decoders' correct function. This allows a complete test of the memory's decoders with only minimal time.
(FR) L'invention concerne la structure et la conception d'une mémoire non volatile, en particulier de mémoires incorporées ou intégrées dans des circuits intégrés. L'objectif de cette invention est de résoudre le problème des temps d'essai excessifs pour ce type de mémoires, en particulier en matière d'essai de décodeurs associés. A cet effet, un nombre prédéterminé de cellules de mémoire non volatile, qui dépend de la taille de la mémoire, sont modifiées en cellules de mémoire ROM à modèle de contenu fixe. Ces cellules ROM supplémentaires étant simplement des cellules non volatiles modifiées, elles ne diffèrent que légèrement de ces dernières. Ainsi, elles ne nécessitent pas beaucoup d'efforts en matière de fabrication et, ce qui est encore plus important, n'occupent qu'un faible espace supplémentaire sur la puce mémoire ou le circuit intégré, tout en fournissant un avantage significatif en matière d'essai. Lorsque des paires de cellules de mémoire non volatile sensiblement asymétriques sont utilisées, chaque paire présentant une ligne binaire commune, le retrait ou l'interruption de ce contact au niveau de la ligne binaire peut servir à inscrire une valeur fixe, p. ex. un '0', dans cette paire et vice versa. Au cours de l'essai, un motif simple et ne nécessitant ainsi qu'une durée minimale, de préférence un motif en damier, est écrit dans la mémoire non volatile et lu à partir de cette dernière, ce qui permet de déterminer rapidement le bon fonctionnement des décodeurs. On peut ainsi réaliser un essai complet des décodeurs de mémoire pendant une durée minimale.
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