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Machine translation
1. (WO2003001530) ERASE METHOD FOR DUAL BIT VIRTUAL GROUND FLASH
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2003/001530    International Application No.:    PCT/US2002/007641
Publication Date: 03.01.2003 International Filing Date: 14.03.2002
IPC:
G11C 16/04 (2006.01), G11C 16/16 (2006.01)
Applicants: ADVANCED MICRO DEVICES, INC. [US/US]; One AMD Place P.O. Box 3453, Mail Stop 68 Sunnyvale, CA 94088-3453 (US)
Inventors: HAMILTON, Darlene, G.; (US).
TANPAIROJ, Kulachet; (US).
WU, Yider; (US)
Agent: RODDY, Richard, J.; Advanced Micro Devices, Inc. Mail Stop 68 One AMD Place Sunnyvale, CA 94088-3453 (US)
Priority Data:
09/886,861 21.06.2001 US
Title (EN) ERASE METHOD FOR DUAL BIT VIRTUAL GROUND FLASH
(FR) PROCEDE D'EFFACEMENT POUR MEMOIRE FLASH A MASSE VIRTUELLE A BITS DOUBLES
Abstract: front page image
(EN)A system and methodology is provided for verifying erasure of one or more dual bit virtual ground memory cells (10, 82, 84, 86, 88) in a memory device, such as a flash memory. Each of the dual bits (10, 82, 84, 86, 88) has a first or normal bit and a second or complimentary bit associated with the first or normal bit. The system and methodology include verifying and erasure of both a normal bit and a complimentary bit of the cell. The erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell. The set of erase pulses is comprised of a two sided erase pulse to both sides of the bits in the cell or transistor junction followed by a first single sided erase pulse to one side and a second single sided erase pulse to the other side of transistor junction.
(FR)L'invention concerne un système et une technique permettant de vérifier l'effacement d'une ou de plusieurs cellules de mémoire à masse virtuelle à bits doubles (10, 82, 84, 86, 88) dans un dispositif mémoire tel qu'une mémoire flash. Chacun des bits doubles (10, 82, 84, 86, 88) comporte un premier bit, ou bit normal, et un second bit, ou bit complémentaire, associé au bit normal. Ce système et cette technique permettent de vérifier un effacement d'un bit normal et d'un bit complémentaire de la cellule. L'effacement consiste à appliquer un ensemble d'impulsions d'effacement sur le bit normal et le bit complémentaire dans une cellule à bits doubles unique. L'ensemble d'impulsions d'effacement est constitué d'une impulsion d'effacement double destinée aux deux côtés des bits dans la cellule ou la jonction de transistor, puis d'une première impulsion d'effacement simple pour un côté et d'une seconde impulsion d'effacement simple pour l'autre côté de la jonction de transistor.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, OM, PH, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZM, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)