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Machine translation
1. (WO2003001529) METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY REDUNDANCY SYSTEM
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2003/001529    International Application No.:    PCT/IB2002/002334
Publication Date: 03.01.2003 International Filing Date: 18.06.2002
IPC:
G11C 29/00 (2006.01)
Applicants: KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL/NL]; Groenewoudseweg 1, NL-5621 BA Eindhoven (NL) (For All Designated States Except US).
SALTERS, Roelof, H., W. [NL/NL]; (NL) (For US Only).
CUPPENS, Roger [BE/NL]; (NL) (For US Only).
DITEWEG, Anthonie, M., H. [NL/NL]; (NL) (For US Only)
Inventors: SALTERS, Roelof, H., W.; (NL).
CUPPENS, Roger; (NL).
DITEWEG, Anthonie, M., H.; (NL)
Agent: DE JONG, Durk, J.; Internationaal Octrooibureau B.V., Prof. Holstlaan 6, NL-5656 AA Eindhoven (NL)
Priority Data:
01202407.1 21.06.2001 EP
Title (EN) METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY REDUNDANCY SYSTEM
(FR) PROCEDE ET AGENCEMENT DE CIRCUIT PERMETTANT DE RECUPERER UNE ERREUR DE MEMOIRE
Abstract: front page image
(EN)The present invention relates to a method and circuit arrangement for performing an error recovery in a memory arrangement comprising at least two separate memories. The memory arrangement comprises a central storage for storing a faulty-address information of the at least two separate memories. Each memory has its own local address comparison unit and local volatile memory for addresses. The faulty-address information is transported from the central storage to the local volatile memories for address comparison of a redundancy system. Thereby, overhead and complexity can be reduced and flexibility of the architecture enhanced.
(FR)L'invention concerne un procédé et un agencement de circuit permettant de récupérer une erreur dans un agencement de mémoire comprenant au moins deux mémoires séparées. Ledit agencement de mémoire comprend un stockage central destiné à stocker des informations d'adresses de panne des deux mémoires séparées. Chaque mémoire comprend sa propre unité de comparaison d'adresses locale et une mémoire volatile locale destinée aux adresses. Les informations d'adresses de panne sont transportées du stockage central vers les mémoires volatiles locales afin de comparer les adresses d'un système de redondance. Il est ainsi possible de réduire la surcharge et la complexité de l'architecture de mémoire et de l'améliorer.
Designated States: CN, JP, KR, US.
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR).
Publication Language: English (EN)
Filing Language: English (EN)