WO2003001381 METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR PROCESSING

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Publication Number WO/2003/001381

Publication Date 03.01.2003

International Application No. PCT/IB2002/002333

International Filing Date 18.06.2002

IPC

CPC

Applicants

KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL]/[NL] (AllExceptUS)
DITEWIG, Anthonie, M., H. [NL]/[NL] (UsOnly)
CUPPENS, Roger [BE]/[NL] (UsOnly)
SALTERS, Roelof, H., W. [NL]/[NL] (UsOnly)

Inventors

DITEWIG, Anthonie, M., H.
CUPPENS, Roger
SALTERS, Roelof, H., W.

Agents

DE JONG, Durk, J.

Priority Data

01202406.3

21.06.2001

Publication Language English (en)

Filing Language English (EN)

Designated States

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Title

(EN) METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR PROCESSING

(FR) PROCEDE ET CONFIGURATION DE CIRCUIT UTILISES POUR TRAITER UNE ERREUR DE MEMOIRE

Abstract

(EN) The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.

(FR) L'invention concerne une configuration de circuit et un procédé permettant de réaliser une correction d'erreur dans un assemblage de mémoire dans lequel on utilise un système de redondance. Les adresses des cellules défectueuses sont enregistrées de manière redondante en appliquant un codage correspondant. Ensuite, on applique une correction d'erreur aux informations d'adresse défectueuse avant de les comparer à l'adresse appliquée à l'extérieur. Ainsi, on peut éviter les erreurs dues aux adresses de redondance défectueuses.

G	PHYSICS
06	COMPUTING; CALCULATING OR COUNTING
F	ELECTRIC DIGITAL DATA PROCESSING
11	Error detection; Error correction; Monitoring
07	Responding to the occurrence of a fault, e.g. fault tolerance
08	Error detection or correction by redundancy in data representation, e.g. by using checking codes
10	Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
29	Checking stores for correct operation; Testing stores during standby or offline operation

G	PHYSICS
06	COMPUTING; CALCULATING OR COUNTING
F	ELECTRIC DIGITAL DATA PROCESSING
11	Error detection; Error correction; Monitoring
07	Responding to the occurrence of a fault, e.g. fault tolerance
08	Error detection or correction by redundancy in data representation, e.g. by using checking codes
10	Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
29	Checking stores for correct operation; Testing stores during standby or offline operation

G	PHYSICS
06	COMPUTING; CALCULATING; COUNTING
F	ELECTRIC DIGITAL DATA PROCESSING
11	Error detection; Error correction; Monitoring
07	Responding to the occurrence of a fault, e.g. fault tolerance
08	Error detection or correction by redundancy in data representation, e.g. by using checking codes
10	Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008	in individual solid state devices
1012	using codes or arrangements adapted for a specific type of error
1016	Error in accessing a memory location, i.e. addressing error

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1. WO2003001381 - METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR PROCESSING