Processing

Please wait...

Settings

Settings

Goto Application

1. WO2003001381 - METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR PROCESSING

Publication Number WO/2003/001381
Publication Date 03.01.2003
International Application No. PCT/IB2002/002333
International Filing Date 18.06.2002
IPC
G06F 11/10 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/00 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
CPC
G06F 11/1016
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1012using codes or arrangements adapted for a specific type of error
1016Error in accessing a memory location, i.e. addressing error
G11C 29/00
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
G11C 29/785
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
70Masking faults in memories by using spares or by reconfiguring
78using programmable devices
785with redundancy programming schemes
Applicants
  • KONINKLIJKE PHILIPS ELECTRONICS N.V. [NL]/[NL] (AllExceptUS)
  • DITEWIG, Anthonie, M., H. [NL]/[NL] (UsOnly)
  • CUPPENS, Roger [BE]/[NL] (UsOnly)
  • SALTERS, Roelof, H., W. [NL]/[NL] (UsOnly)
Inventors
  • DITEWIG, Anthonie, M., H.
  • CUPPENS, Roger
  • SALTERS, Roelof, H., W.
Agents
  • DE JONG, Durk, J.
Priority Data
01202406.321.06.2001EP
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR PROCESSING
(FR) PROCEDE ET CONFIGURATION DE CIRCUIT UTILISES POUR TRAITER UNE ERREUR DE MEMOIRE
Abstract
(EN) The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.
(FR) L'invention concerne une configuration de circuit et un procédé permettant de réaliser une correction d'erreur dans un assemblage de mémoire dans lequel on utilise un système de redondance. Les adresses des cellules défectueuses sont enregistrées de manière redondante en appliquant un codage correspondant. Ensuite, on applique une correction d'erreur aux informations d'adresse défectueuse avant de les comparer à l'adresse appliquée à l'extérieur. Ainsi, on peut éviter les erreurs dues aux adresses de redondance défectueuses.
Latest bibliographic data on file with the International Bureau