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1. (WO2002103767) EPITAXIAL SIO¿X? BARRIER/INSULATION LAYER______________________
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2002/103767 International Application No.: PCT/US2001/040970
Publication Date: 27.12.2002 International Filing Date: 14.06.2001
Chapter 2 Demand Filed: 08.01.2003
IPC:
H01L 21/762 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
Applicants:
NANODYNAMICS, INC. [US/US]; 510 E. 73rd Street New York, NY 10021, US (AllExceptUS)
WANG, Chia-Gee [US/US]; US (UsOnly)
TSU, Raphael [US/US]; US (UsOnly)
LOFGREN, John, Clay [US/US]; US (UsOnly)
Inventors:
WANG, Chia-Gee; US
TSU, Raphael; US
LOFGREN, John, Clay; US
Agent:
HANDELMAN, Joseph, H. ; Ladas & Parry 26 West 61st Street New York, NY 10023, US
Priority Data:
Title (EN) EPITAXIAL SIOX BARRIER/INSULATION LAYER______________________
(FR) COUCHE BARRIERE OU ISOLANTE EPITAXIALE EN SIOX
Abstract:
(EN) A method for producing an insulating or barrier layer (Fig. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on said deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite. Semiconductor devices are disclosed which comprise said barrier composite.
(FR) L'invention concerne un procédé de production d'une couche barrière ou isolante (fig. 1B), utile pour des dispositifs à semi-conducteurs. Le procédé consiste à déposer une couche de silicium et au moins un élément supplémentaire sur un substrat de silicium, ladite couche déposée étant sensiblement exempte de défauts afin qu'un silicium épitaxial sensiblement exempt de défauts puisse être déposé sur la couche déposée. Dans une autre forme de réalisation, une monocouche d'un ou de plusieurs éléments, de préférence comprenant oxygène, est absorbée sur un substrat de silicium. Plusieurs couches isolantes prises en sandwich entre un silicium épitaxial forment un composite barrière. L'invention concerne en outre des dispositifs à semi-conducteurs comprenant ce composite barrière.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)