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1. (WO2002082551) A SEMICONDUCTOR STRUCTURE EXHIBITING REDUCED LEAKAGE CURRENT
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2002/082551 International Application No.: PCT/US2001/048805
Publication Date: 17.10.2002 International Filing Date: 18.12.2001
IPC:
H01L 29/51 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
51
Insulating materials associated therewith
Applicants:
MOTOROLA, INC. [US/US]; 1303 East Algonquin Road Schaumburg, IL 60196, US
Inventors:
YU, Zhiyi; US
DROOPAD, Ravindranath; US
EISENBEISER, Kurt, W.; US
Agent:
KOCH, William, E.; Motorola Labs 3102 North 56th Street AZ11/56-238 Phoenix, AZ 85018-6606, US
Priority Data:
09/824,25902.04.2001US
Title (EN) A SEMICONDUCTOR STRUCTURE EXHIBITING REDUCED LEAKAGE CURRENT
(FR) STRUCTURE DE SEMI-CONDUCTEUR A COURANT DE FUITE ATTENUE
Abstract:
(EN) A semiconductor structure exhibiting reduced leakage current is formed of a monocrystalline substrate (101) and a strained-layer heterostructure (105).The strained-layer heterostructure has a first layer (102) formed of a first monocrystalline oxide material having a first lattice constant and a second layer (104) formed of a second monocrystalline oxide material overlying the first layer and having a second lattice constant.The second lattice constant is different from the first lattice constant. The second layer creates strain within the oxide material layers, at the interface between the first and second oxide material layers of the heterostructure, and at the interface of the substrate and the first layer, which changes the energy band offset at the interface of the substrate and the first layer.
(FR) La présente invention concerne une structure de semi-conducteur à courant de fuite atténué fait d'un substrat monocristallin (101) et d'une hétérostructure en couches contraintes (105). Cette hétérostructure en couches contraintes comporte une première couche (102) d'un premier oxyde monocristallin caractérisé par une première constante de réseau et une seconde couche (104) d'un second oxyde monocristallin caractérisé par une seconde constante de réseau différente de la première constante de réseau. La seconde couche crée une contrainte entre les couches d'oxydes, d'une part à l'interface entre les deux couches d'oxyde de l'hétérostructure, et d'autre part à l'interface entre le substrat et la première couche, ce qui modifie le décalage des bandes d'énergie part à l'interface entre le substrat et la première couche.
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Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PH, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW
African Regional Intellectual Property Organization (ARIPO) (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)