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1. WO2002041290 - METHOD AND APPARATUS FOR INCREASING THE RESOLUTION OF A NON-CRT VIDEO DISPLAY

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[ EN ]

METHOD AND APPARATUS FOR INCREASING THE RESOLUTION
OF A NON-CRT VIDEO DISPLAY

TECHNICAL FIELD
The present invention relates to a method and an apparatus to increase the resolution of non-CRT video display without increasing the bandwidth required and especially the pixel clock rate.

BACKGROUND OF THE INVENTION
Video signals, generated by a computer or other source, for displaying on a video display are well known in the art. Typically, in the prior art, the video signal supplied to a video display has operated in the frequency range of at least 60 Hz or greater as the frame rate. For a CRT, the frame rate is characterized by the frequency of the vertical sync or VSYNC pulse. Further, heretofore, the prior art has not recognized the difference between the affect of a video signal being displayed on different types of video displays. Therefore, heretofore, the same type of video signal has been used to be displayed on a CRT as well as non-CRT displays. As used herein, a CRT display is a display characterized by an electron beam traversing in a vacuum tube impinging on a phosphorous screen to cause the emission of light from the phosphor. A non-CRT display includes but is not limited to a thin film transistor (TFT) liquid crystal display (TFT/LCD) or a STN (Super Twisted Neimatic) liquid crystal display (STN/LCD) or a plasma display, or a Field Emission Device (FED) display, or an organic light emitting diode (OLED) display, or an LCD on silicon-type display. All of these types of displays as used herein shall be referred to as non-CRT display.

Referring to Figure 1 there is shown a schematic timing diagram of a method of the prior art to increase the resolution of a video signal for display on a non-CRT device. As previously discussed, in the prior art, no distinction was made between a CRT device and a non-CRT device. Therefore, the discussion set forth below is equally used for the display of a video signal on a CRT display. However, the present invention relates to increasing the resolution of a video signal for display on a non-CRT type display.
Figure 1 shows a video signal having a VSYNC pulse which signifies the beginning of a video frame. From one VSYNC pulse (VSYNC 1) to the next VSYNC pulse (VSYNC2) represents the signals being displayed on one video frame. Within two consecutive VSYNC pulses are a plurality of HSYNC pulses (designated as HSYNC1, HSYNC2 ...). Each
HSYNC pulse represents a pulse signal to signify to the display device the beginning of the display on a horizontal line. Finally, within each consecutive HSYNC pulse are a plurality of pixel signals representing the actual data signal to be displayed on the display device. All of the above has been described with reference to VSYNC and HSYNC pulses which are typically terms used to reference a video signal for display on a CRT device; the same concept is also used for non-CRT display. For non-CRT display, the VSYNC pulse is typically referred to as a new frame signal and the HSYNC signal is typically referred to as a new line signal. For the purpose of the discussion set forth herein, the term VSYNC and HSYNC wiil continue to be used even though they also include the equivalent of new frame signal or new line signal respectively.
Again, referring to Figure 1, there is shown a method of the prior art wherein to increase the resolution of a video signal, one way is to maintain the frequency Fl of the VSYNC pulses but to increase the frequency F2 of the HSYNC pulses. This results in more "lines" per frame. This, of course, also necessitates that the frequency of the pixel signals within each line (if the same numbered pixels are to be maintained) be increased. Thus, one way of increasing the resolution of a video signal in the prior art Is to maintain the VSYNC pulse rate but increase the HSYNC pulse rate and maintain the same number of pixels per horizontal line but increase the pixel clock rate.
One example of the prior art display format is as follows: A video signal designed to be display at 1280 (pixels per line) x 720 (horizontal lines per frame) is operated with a VSYNC rate of 60.73Hz, with an HSYNC rate of 45.055KHz and a pixel clock rate of 74.25MHz. To increase the resolution of the video signal to 1280 x 1024, the pixel clock rate must be increased to 108. MHz, with the VSYNC pulse rate maintained at substantially 60.020Hz and the HSYNC rate increased to 63.981KHz. In the prior art, it has been universally accepted that the VSYNC rate should not fall below 60Hz due to "flickering" problems that might be perceived by the user. In particular, in the prior art, the VSYNC rate has operated as low as greater than 60Hz, to 75Hz, and to 85Hz.
In another variation of the prior art where it is desired to increase the resolution of a video signal, to 1600 x 1200 where both the number of pixels per line and the number of horizontal lines per frame are increased, it has been necessary to increase the pixel clock rate to 162MHz while maintaining the VSYNC rate at 60Hz, and increase the HSYNC rate to 75KHz.

SUMMARY OF THE INVENTION
The present invention is a method of increasing the resolution of a video display of a video signal on a non-CRT display. The video signal has a first frequency between each adjacent pixels and a second frequency between the start of each consecutive video frames. The method of the invention comprises decreasing the second frequency to a third frequency thereby increasing the time between the start of each consecutive video frames. The number of pixels in each video frame is then increased thereby increasing the resolution of the video display.
The present invention also relates to a video display apparatus for displaying a video signal having a plurality of synchronization signals with the first frequency and a plurality of pixel signals therebetween. Each synchronization signal represents the start of a video frame. The video apparatus has means for generating the video signal with the first frequency being less than 60Hz and greater than OHz.- The generated video signal is then supplied to a non-CRT display for displaying the pixel signals.

BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a timing diagram of a method of increasing the resolution of a video display of the prior art.
Figure 2 is a timing diagram of a method of increasing the video display on a non-CRT display by the present invention.
Figure 3 is a schematic block level diagram of an apparatus of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS
Referring to Figure 2 there is shown a timing diagram of the method of the present invention to increase the resolution of a video signal being displayed on a non-CRT display. Similar to Figure 1, the timing diagram in Figure 2 shows a video signal having a plurality of VSYNC signals operating at a frequency of Fl. Between each VSYNC signals is a plurality of HSYNC signals operating at frequency of F3.
In the method of the present invention to increase the resolution of display, the method decreases the frequency of the VSYNC signals. Thus, as shown in Figure 2, the video signal having the increased resolution has a plurality of VSYNC signals operating at a frequency F2 where F2 is less than Fl . Since there is a greater period of time between successive VSYNC signals, either the number of HSYNC signals can be increased or more pixels per line can be displayed.
As a particular example of the method of the present invention, the following parameters of the video signals were used. To display a signal having 1280 x 720 as done conventionally, and as previously disclosed, the pixel clock is operated at 74.25MHz, the VSYNC clock is operated at 60.073Hz, and the HSYNC signal is operated at 45.055KHz. To display a video signal on a non-CRT display having a resolution of 1280 x 1024, the pixel clock in a preferred embodiment is maintained the same at 74.25MHz. The HSYNC signal is operated at 49.899KHz. The frequency of the VSYNC signal is then operated at 48.026Hz. In another embodiment, the same resolution can be operated with a pixel clock rate of 84MHz, HSYNC signal of 49J63KHz, and a VSYNC signal of 46.682Hz. A third embodiment for displaying a video signal at a resolution of 1280 x 1024 on a non-CRT display is to operate the pixel clock at 74.176MHz, the HSYNC signal at 49.849KHz, and VSYNC signal at 47.978Hz.
To further increase the resolution of a video signal, operating at, for example, 1600 x 1200 resolution, the preferred embodiment is to maintain the pixel clock at 74.25MHz. The HSYNC signal is then operated at 41.067KHz with VSYNC signal operating at 33.8Hz.
Another embodiment to display a video signal having 1600 x 1200 resolution on a non-CRT display is to operate the pixel clock at 74.176MHz, the HSYNC signal at 41.026KHz, and the VSYNC signal at 33J67Hz.
In the preferred method of the present invention, to increase the resolution of a video signal, the VSYNC rate is dropped below 60Hz but greater than OHz. Further, it is preferred to operate in the range of 5 OHz to 10Hz with a preferred signal range of 20 to 3 OHz with a signal rate of 24Hz (which is the frame rate for movies) as being preferred. Finally, it is preferred to have the same pixel clock rate used for all of the different resolutions.
As shown and described in Figure 2, one way to increase the resolution of video display is to decrease the VSYNC frequency thereby permitting more horizontal lines to be inserted in each video frame, with the preferred embodiment of the pixel clock rate being maintained the same. In another embodiment of the present invention, the frequency of the VSYNC signal can be decreased with the HSYNC signal frequency also decreased permitting more pixels per line to be displayed in a single horizontal line.
Referring to Figure 3 there is shown a block level diagram of an apparatus 10 of the present invention. In the apparatus 10, a CPU 18 generate the pixel data to be displayed on a non-CRT display device 20. The pixel data is then clocked by a pixel clock to a video memory 12 where they are stored. The pixel signals stored in the video memory 12 are then clocked out of the video memory 12 into a mixer 14. Another input to the mixer 14 is the output of an HSYNC and VSYNC signal generator 16. The HSYNC and VSYNC signal generator 16 generates the HSYNC and VSYNC signals with the VSYNC signal generator portion of 16 operating at less than 60Hz. The HSYNC and VSYNC so generated are then mixed by the mixer 14 with the pixel signals from the video memory 12 and are received by the non-CRT video display 20 where the pixel signals from the video memory 12 are displayed.
The theory of the present invention is as follows. It has been found that for a non-CRT display, there is a long period of persistence which permits a video pixel signal to be displayed at a particular location on the non-CRT display and for that signal to persist. In fact, it has been found, for example, for TFT/LCD display, the persistence is typically 40 - 50M seconds which equates to a response time of 20Hz. Thus, the video signal may be refreshed at a rate as low as 20Hz without deleterious or flickering affect being noticeable. Conversely, by increasing the frequency of the video signal supplied to a non-CRT display beyond its persistence frequency, one actually does not increase the resolution. This is because the non-CRT display device is unable to respond as quickly to the change in the video signal supplied to it. In effect, any increase in the frequency of the video signal supplied to such a device beyond its persistence frequency means that the bandwidth is wasted.
The VESA standard, which is a well-known standard, dictates that a non-volatile memory be placed in a display device showing the capabilities of the display device to display in different resolutions. In the preferred embodiment, the capability of the non-CRT display to receive video signals at a rate below 60Hz may be stored in the non- volatile memory portion that is associated with the display device. Thus, when the CPU 18 to which the display device 20 is connected polls or queries the non- volatile memory, it can determine that the particular display device 20 attached to it can display at a frequency which heretofore has not been "permitted" by conventional wisdom.
There are a number of advantages to the method and apparatus of the present invention. In the preferred embodiment where the same pixel clock rate is used for different resolutions, it means that a single standardized pixel clock can be used. Secondly, by decreasing the frequency of the VSYNC rate, this reduces the RF emission. This permits the video signal to be transmitted via a longer cable than otherwise possible. Further, by lowering or reducing the bandwidth requirement, it means that the CPU overhead is decreased freeing the CPU to perform other tasks than to refresh the video memory.