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Machine translation
1. (WO2002028162) PENALTY FREE ADDRESS DECODING SCHEME
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2002/028162    International Application No.:    PCT/SE2001/002862
Publication Date: 11.04.2002 International Filing Date: 20.12.2001
Chapter 2 Demand Filed:    02.07.2003    
IPC:
G06F 12/06 (2006.01)
Applicants: TELEFONAKTIEBOLAGET LM ERICSSON (publ) [SE/SE]; S-164 83 Stockhom (SE) (For All Designated States Except US).
PLESNER, Erik [DK/DK]; (DK) (For US Only)
Inventors: PLESNER, Erik; (DK)
Agent: ERICSSON TELECOM AB; Patent Unit Service and Backbone Networks, S-126 25 Stockholm (SE)
Priority Data:
Title (EN) PENALTY FREE ADDRESS DECODING SCHEME
(FR) SCHEMA DE DECODAGE D'ADRESSE SANS PENALITE
Abstract: front page image
(EN)The present invention relates to an arrangement for addressing a dual-plane memory. The memory has a first signal input used to activate the memory and a second signal input used to address one of the two memory planes. The arrangement comprises a microprocessor that comprises a chip-select generator having a first chip-select output and a second chip-select output. The first output is connected to the first input of the memory and the second output is connected to the second input of the memory. The outputs and the inputs are connected to each other without time critical element in-between.
(FR)L'invention concerne un arrangement permettant d'adresser une mémoire à double plan. La mémoire possède une première entrée de signal utilisée afin d'activer la mémoire et une seconde entrée de signal utilisée afin d'adresser un des deux plans de la mémoire. L'arrangement comprend un microprocesseur qui contient un générateur de validation de circuit comportant une première et une seconde sorties de validation de circuit. La première sortie est reliée à la première entrée de la mémoire et la seconde sortie est reliée à la seconde entrée de la mémoire. Les sorties et les entrées sont connectées les unes aux autres sans élément temporel critique entre elles.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)