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Machine translation
1. (WO2002027795) FULLY SYNTHESISABLE AND HIGHLY AREA EFFICIENT VERY LARGE SCALE INTEGRATION (VLSI) ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2002/027795    International Application No.:    PCT/US2001/030307
Publication Date: 04.04.2002 International Filing Date: 26.09.2001
Chapter 2 Demand Filed:    03.04.2002    
IPC:
H01L 27/02 (2006.01)
Applicants: CONEXANT SYSTEMS, INC. [US/US]; 4311 Jamboree Road, E08-801 Newport Beach, CA 92660 (US) (For All Designated States Except US).
LI, Xiaoming [CA/US]; (US) (For US Only).
TENNYSON, Mark, R. [US/US]; (US) (For US Only).
WORLEY, Eugene, R. [US/US]; (US) (For US Only)
Inventors: LI, Xiaoming; (US).
TENNYSON, Mark, R.; (US).
WORLEY, Eugene, R.; (US)
Agent: SKALE, Andrew, D.; Brobeck, Phleger & Harrison 12390 El Camino Real San Diego, CA 92130 (US).
VIERING, JENTSCHURA & PARTNER; Steinsdorfstrasse 6 D-80538 München (DE)
Priority Data:
09/672,165 27.09.2000 US
Title (EN) FULLY SYNTHESISABLE AND HIGHLY AREA EFFICIENT VERY LARGE SCALE INTEGRATION (VLSI) ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT
(FR) CIRCUIT DE PROTECTION CONTRE LA DECHARGE ELECTROSTATIQUE (ESD) ENTIEREMENT SYNTHESISABLE ET A INTEGRATION DE TRES GRANDE ECHELLE (VLSI) TRES EFFICACE SUR ZONE
Abstract: front page image
(EN)An electrostatic discharge (ESD) protection circuit comprises a P-channel field effect transistor (PFET), a buffer and a damping network to provide improved protection for an integrated circuit against high-voltage ESD pulses. The ESD protection circuit is capable of being fabricated with a reduced surface area layout to be fully synthesisable with the integrated circuit which it is designed to protect.
(FR)L'invention concerne un circuit de protection de décharge électrostatique (ESD) doté d'un transistor à effet de champ canal-P (PFET), une mémoire tampon et un réseau d'atténuation permettant de fournir une protection à un circuit intégré contre des impulsions ESD à haute tension. Le circuit de protection ESD peut être fabriqué avec une conception de zone de surface réduite pour être complètement synthétisé avec le circuit intégré qui est conçu pour protéger.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PH, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)