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Machine translation
1. (WO2002027565) PERFORMANCE LEVEL MODELING AND SIMULATION OF ELECTRONIC SYSTEMS HAVING BOTH HARDWARE AND SOFTWARE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2002/027565    International Application No.:    PCT/US2001/030401
Publication Date: 04.04.2002 International Filing Date: 28.09.2001
Chapter 2 Demand Filed:    24.04.2002    
IPC:
G06F 11/34 (2006.01), G06F 17/50 (2006.01)
Applicants: CADENCE DESIGN SYSTEMS, INC. [US/US]; 2655 Seely Avenue San Jose, CA 95134 (US)
Inventors: SOLDEN, Sherry; (US).
HARCOURT, Edwin, A.; (US).
LARUE, William, W.; (US).
DUNLOP, Douglas, D.; (US).
HOOVER, Christopher; (US).
CHAO, Qizhang; (US).
AGRAWAL, Poonam; (US).
BEVERLY, Aaron; (US).
CHIODO, Massimilano, L.; (US).
BHATNAGAR, Nheeti, K.; (US).
DESAI, Soumya; (IN).
CHOU, Hungming; (US).
SHOLES, Michael, D.; (US).
DENNISON, Ian; (US).
CHAKRAVARTY, Sanjay; (IN).
O'BRIEN-STRAIN, Eamonn; (US).
LAVAGNO, Luciano; (US)
Agent: CARPENTER, John, W.; Crosby, Heafey, Roach & May Two Embarcadero Center Suite 2000 San Francisco, CA 94111 (US)
Priority Data:
09/670,911 28.09.2000 US
Title (EN) PERFORMANCE LEVEL MODELING AND SIMULATION OF ELECTRONIC SYSTEMS HAVING BOTH HARDWARE AND SOFTWARE
(FR) MODELISATION DE NIVEAU DE PERFORMANCE ET SIMULATION DE SYSTEMES ELECTRONIQUES POSSEDANT A LA FOIS DES RESSOURCES MATERIELLES ET DES RESSOURCES LOGICIELLES
Abstract: front page image
(EN)A method and system for evaluating performance level models of electronic systems having both hardware and software, and allowing for the implementation and testing of different architectural designs for compliance with desired operational requirements. Behavior and architecture are captured (Steps 10 and 15) and mapped to architectural components (Step 20). The mapped system is simulated (Step 25), hardware and software components are exported (Step 30), and both hardware and software components are separately verfied (Steps 35-50), and the resulting system is verified using a co-verification tool (Step 55).
(FR)L'invention concerne un procédé et un système d'évaluation de modèles de niveau de performance de systèmes électroniques possédant à la fois des ressources matérielles et des ressources logicielles, et permettant la mise en oeuvre et l'essai de différentes conceptions architecturales de manière que celles-ci soient conformes aux exigences de fonctionnement. Le comportement et l'architecture sont saisis (étapes 10 et 15) et mappés sur des composants architecturaux (étape 20). Le système mappé est simulé (étape 25), les composants matériels et logiciels sont exportés (étape 30), et ces derniers sont vérifiés séparément (étapes 35.50), le système qui en résulte est ensuite vérifié au moyen d'un outil de co-vérification (étape 55).
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PH, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)