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1. WO2002025818 - A LOW JITTER HIGH SPEED CMOS TO CML CLOCK CONVERTER

Publication Number WO/2002/025818
Publication Date 28.03.2002
International Application No. PCT/US2001/029028
International Filing Date 18.09.2001
Chapter 2 Demand Filed 24.03.2003
IPC
D04H 13/00 2006.01
DTEXTILES; PAPER
04BRAIDING; LACE-MAKING; KNITTING; TRIMMINGS; NON-WOVEN FABRICS
HMAKING TEXTILE FABRICS, e.g. FROM FIBRES OR FILAMENTARY MATERIAL; FABRICS MADE BY SUCH PROCESSES OR APPARATUS, e.g. FELTS, NON-WOVEN FABRICS; COTTON-WOOL; WADDING
13Other non-woven fabrics
H03K 19/0185 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175Coupling arrangements; Interface arrangements
0185using field-effect transistors only
CPC
H03K 19/018514
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0175Coupling arrangements; Interface arrangements
0185using field effect transistors only
018507Interface arrangements
018514with at least one differential stage
H03K 19/018528
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
0175Coupling arrangements; Interface arrangements
0185using field effect transistors only
018507Interface arrangements
018521of complementary type, e.g. CMOS
018528with at least one differential stage
H03K 5/1565
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulating of pulses not covered by one of the other main groups of this subclass
156Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
1565the output pulses having a constant duty cycle
Applicants
  • BROADCOM CORPORATION [US]/[US]
Inventors
  • CHOI, Ka, Lun
Agents
  • SOKOHL, Robert
Priority Data
60/223,18115.09.2000US (Considered void 06.05.2002)
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) A LOW JITTER HIGH SPEED CMOS TO CML CLOCK CONVERTER
(FR) CONVERTISSEUR D'HORLOGE CMOS-CML A GRANDE VITESSE ET FAIBLE INSTABILITE
Abstract
(EN)
Provided is a circuit to convert input CMOS level signals having a predetermined duty cycle to CML level signals having a higher duty cycle. The circuit includes two differential transistor pairs are constructed and arranged to uses gates of the associated transistors as inputs to receive and combine a number of phase shifted CMOS input signals. The combined CMOS input signal are converted to CML level signals which are provided as circuit outputs.
(FR)
L'invention concerne un circuit destiné à transformer des signaux d'entrée de niveau CMOS, qui présentent un cycle d'utilisation prédéterminé, en signaux de niveau CML présentant un cycle d'utilisation supérieur. Le circuit comprend deux paires de transistors différentiels connectés entre eux. Ces paires différentielles sont conçues pour utiliser des grilles des transistors associés comme entrées afin de recevoir et combiner des signaux d'entrée CMOS déphasés. Les signaux d'entrée CMOS combinés sont transformés en signaux de niveau CML, qui sont produits comme signaux de sortie du circuit.
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