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1. WO2002023627 - SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD OF FABRICATION

Publication Number WO/2002/023627
Publication Date 21.03.2002
International Application No. PCT/US2001/026646
International Filing Date 24.08.2001
Chapter 2 Demand Filed 12.04.2002
IPC
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532characterised by the materials
CPC
H01L 21/76843
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76841Barrier, adhesion or liner layers
76843formed in openings in a dielectric
H01L 21/76876
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76841Barrier, adhesion or liner layers
76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
76876for deposition from the gas phase, e.g. CVD
H01L 21/76885
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
H01L 23/5226
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
5226Via connections in a multilevel interconnection structure
H01L 23/5329
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532characterised by the materials
5329Insulating materials
H01L 23/53295
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532characterised by the materials
5329Insulating materials
53295Stacked insulating layers
Applicants
  • INFINEON TECHNOLOGIES NORTH AMERICA CORP. [US]/[US]
  • INTERNATIONAL BUSINESS MACHINES CORPORATION [US]/[US]
Inventors
  • IGGULDEN, Roy
  • WEBER, Stefan
Agents
  • BRADEN, Stanton, C.
Priority Data
09/662,42414.09.2000US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD OF FABRICATION
(FR) STRUCTURE DE SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
Abstract
(EN)
High aspect ratio vias formed in a first insulating layer are filled with conductors in a manner that both reduces the number of processing steps and allows an alignment tool (stepper) to align to alignment and overlay marks. Sidewalls and a bottom of each via are coated with titanium, titanium nitride, and a chemical vapor deposited seed layer of aluminum. A physical vapor deposited layer of aluminum is then formed while the structure is heated to about 400 degrees C to completly fill the vias and to overfill same to form a blanket layer of aluminum above the first insulating layer (34). The blanket layer of aluminum is then patterned and etched to result in columns of aluminum. A second insulating layer is then formed around the columns of aluminum. The ends of the columns at a top of the second insulating layer lie in a relatively common plane to which steppers can relatively easily align patterns.
(FR)
Des trous d'interconnexion à rapport d'aspect élevé formés dans une première couche d'isolation recouvrant un substrat (corps) de semi-conducteur sont remplis de conducteurs, de sorte que le nombre d'étapes de traitement peut être réduit et qu'un outil d'alignement (graveur à répétition) peut s'aligner sur des repères d'alignement et de recouvrement. Les parois latérales et le fond de chaque trou d'interconnexion sont recouverts d'une couche composite de titane, de nitrure de titane, et d'une couche d'ensemencement d'aluminium déposée en phase vapeur. Une couche physique d'ensemencement d'aluminium déposée en phase vapeur est ensuite formée pendant que la structure est chauffée jusqu'à environ 400 degrés C afin de remplir complètement les trous de connexion, et de déborder jusqu'à former une couche de couverture d'aluminium sur la première couche d'isolation (34). Des motifs sont ensuite formés dans ladite couche de couverture d'aluminium qui est gravée afin de produire des colonnes d'aluminium. Une seconde couche d'isolation est ensuite formée autour desdites colonnes d'aluminium. Les extrémités de ces colonnes,au niveau de la partie supérieure de la seconde couche d'isolation, s'étendent dans un plan relativement commun dans lequel les graveurs à répétition peuvent relativement facilement aligner des motifs.
Also published as
Latest bibliographic data on file with the International Bureau