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1. WO2002021775 - PLURAL STATION MEMORY DATA SHARING SYSTEM

Publication Number WO/2002/021775
Publication Date 14.03.2002
International Application No. PCT/JP2001/007483
International Filing Date 30.08.2001
IPC
H04J 3/06 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
02Details
06Synchronising arrangements
H04L 12/417 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
28characterised by path configuration, e.g. LAN or WAN
40Bus networks
407with decentralised control
417with deterministic access, e.g. token passing
H04L 29/06 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
29Arrangements, apparatus, circuits or systems, not covered by a single one of groups H04L1/-H04L27/136
02Communication control; Communication processing
06characterised by a protocol
CPC
H04J 3/0652
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
JMULTIPLEX COMMUNICATION
3Time-division multiplex systems
02Details
06Synchronising arrangements
0635Clock or time synchronisation in a network
0638Clock or time synchronisation among nodes; Internode synchronisation
0652Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP]
H04L 12/417
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
12Data switching networks
28characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
40Bus networks
407with decentralised control
417with deterministic access, e.g. token passing
H04L 69/28
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
69Application independent communication protocol aspects or techniques in packet data networks
28Timer mechanisms used in protocols
Applicants
  • KOYO ELECTRONICS INDUSTRIES CO., LTD. [JP]/[JP] (AllExceptUS)
  • STEP TECHNICA CO., LTD. [JP]/[JP] (AllExceptUS)
  • MUGITANI, Tomihiro [JP]/[JP] (UsOnly)
  • NATSUI, Toshiki [JP]/[JP] (UsOnly)
Inventors
  • MUGITANI, Tomihiro
  • NATSUI, Toshiki
Agents
  • SAWADA, Masao
Priority Data
2000-26539601.09.2000JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) PLURAL STATION MEMORY DATA SHARING SYSTEM
(FR) SYSTÈME DE PARTAGE DE DONNÉES MÉMOIRE DE PLUSIEURS STATIONS
Abstract
(EN)
A plural station memory data sharing system in which packets are sent/received between plural stations interconnected through communication lines. Each station has a unique station address value, and the time is made to correspond to each station address value. The internal clock (39) in each station indicates the same time and circulates from time T00 to an upper limit time TM. When the internal clock (39) indicates a time corresponding to the station address value of a station, data stored in a memory at the address position corresponding to the station address value is buried in a packet and the packet is sent through a communication line. An allowance time error sensing circuit (34) compares the calculated correct time of the internal clock of the station and the time indicated by the internal clock. If the error is out of an allowance range, the internal clock (39) is forcedly calibrated to the correct time.
(FR)
L'invention concerne un système de partage de données mémoire de plusieurs stations, dans lequel des paquets sont envoyés /reçus entre plusieurs stations reliées entre elles par des lignes de communication. Chaque station possède une valeur adresse de station unique, l'heure étant prévue de manière à correspondre à la valeur adresse de chaque station. L'horloge interne (39) de chaque station indique la même heure et circule entre l'heure T00 et une heure limite supérieure TM. Lorsque l'horloge interne (39) indique une heure correspondant à la valeur adresse d'une station, les données stockées dans une mémoire à la position d'adresse correspondant à la valeur adresse de la station sont enfouies dans un paquet, lequel est envoyé sur une ligne de communication. Un circuit de détection de tolérance d'erreur de synchronisation (34) compare l'heure de correction calculée de l'horloge interne de la station à l'heure indiquée par l'horloge interne. Si l'erreur se situe hors d'une plage de tolérance, on force l'étalonnage de l'horloge interne (39) à l'heure correcte.
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