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1. WO2002019525 - PROTECTION FOR INPUT BUFFERS OF FLASH MEMORIES

Publication Number WO/2002/019525
Publication Date 07.03.2002
International Application No. PCT/US2001/010001
International Filing Date 28.03.2001
Chapter 2 Demand Filed 27.03.2002
IPC
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
H03K 19/003 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
003Modifications for increasing the reliability
CPC
G11C 2207/2227
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
22Control and timing of internal memory operations
2227Standby or low power modes
G11C 7/1078
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
G11C 7/1084
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
1084Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
H03K 19/00315
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
003Modifications for increasing the reliability ; for protection
00315in field-effect transistor circuits
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US] (AllExceptUS)
  • MAROTTA, Giulio-Giuseppe [IT]/[IT] (UsOnly)
  • D'AMBROSIO, Elio [IT]/[IT] (UsOnly)
Inventors
  • MAROTTA, Giulio-Giuseppe
  • D'AMBROSIO, Elio
Agents
  • VIKSNINS, Ann, S.
Priority Data
09/651,47830.08.2000US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) PROTECTION FOR INPUT BUFFERS OF FLASH MEMORIES
(FR) PROTECTION DE MEMOIRES TAMPONS D'ENTREE DE MEMOIRES FLASH
Abstract
(EN)
An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input buffer includes an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal, and the drain is receptive to an input signal. The input stage inhibits the input signal from being presented at the source of the input stage when the inhibiting signal is at a predetermined level. The input buffer further includes an output stage having an inverter that includes a first connection and a second connection. The first connection couples to the source of the input stage, and the second connection presents the input signal to a low-voltage flash memory device.
(FR)
L'invention concerne une mémoire tampon d'entrée, laquelle empêche le claquage semi-conducteur des transistors à mince couche d'oxyde de grille, dans des circuits intégrés basse tension. Un aspect de la mémoire tampon d'entrée comprend un étage d'entrée comportant une grille, un drain et une source. La grille de l'étage d'entrée est sensible à un signal d'empêchement, et le drain est sensible à un signal d'entrée. L'étage d'entrée empêche le signal d'entrée d'être présenté à la source de l'étage d'entrée lorsque le signal d'empêchement se situe à un niveau déterminé. La mémoire tampon d'entrée comprend encore un étage de sortie possédant un onduleur, lequel comprend une première et une seconde connexion. La première connexion est couplée à la source de l'étage d'entrée, et la seconde présente le signal d'entrée à un dispositif de mémoire flash basse tension.
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