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1. (WO2002009160) PIEZOELECTRIC STRUCTURES FOR ACOUSTIC WAVE DEVICES AND MANUFACTURING PROCESSES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2002/009160    International Application No.:    PCT/US2001/022747
Publication Date: 31.01.2002 International Filing Date: 19.07.2001
Chapter 2 Demand Filed:    03.12.2001    
IPC:
H01L 27/20 (2006.01), H01L 41/22 (2013.01), H03H 3/02 (2006.01), H03H 3/08 (2006.01), H03H 9/02 (2006.01), H03H 9/05 (2006.01), H03H 9/17 (2006.01)
Applicants: MOTOROLA, INC. [US/US]; 1303 East Algonquin Road Schaumburg, IL 60196 (US)
Inventors: FINDER, Jeffrey, M.; (US).
EISENBEISER, Kurt; (US).
RAMDANI, Jamal; (US).
DROOPAD, Ravindranath; (US).
OOMS, William, Jay; (US)
Agent: KOCH, William, E.; Motorola, INC, Motorola Labs Intellectual property Department AZ 11/56-238 3102 North 56th Street Phoenix, AZ 85018-6697 (US)
Priority Data:
09/624,803 24.07.2000 US
Title (EN) PIEZOELECTRIC STRUCTURES FOR ACOUSTIC WAVE DEVICES AND MANUFACTURING PROCESSES
(FR) DISPOSITIF A ONDES ACOUSTIQUES
Abstract: front page image
(EN)High quality epitaxial layers (26) of piezoelectric material materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer (24) on a silicon wafer (22). The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. The piezoelectric films can be used for bulk or surface acoustic wave devices.
(FR)On peut effectuer la croissance de couches épitaxiales de haute qualité (26) de substances en matière piézo-électrique recouvrant de larges tranches de silicium par la croissance préalable d'une couche tampon d'adaptation (24) sur la tranche de silicium (22). La couche tampon d'adaptation est une couche de silice monocristalline séparé de la tranche de silicium par une couche d'interface amorphe (28) de silice. La couche d'interface amorphe dissipe la contrainte et permet la croissance d'une couche tampon d'adaptation d'oxyde monocristalline de haute qualité. Tout décalage de réseaux entre la couche tampon d'adaptation et le substrat de silicium sous-jacent est pris en charge par la couche d'interface amorphe.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)