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1. (WO2002003422) INTEGRATED CIRCUITS PACKAGING SYSTEM AND METHOD

Pub. No.:    WO/2002/003422    International Application No.:    PCT/US2001/020727
Publication Date: Jan 10, 2002 International Filing Date: Jun 29, 2001
IPC: H05K 7/02
Applicants: ALPINE MICROSYSTEMS, INC.
Inventors: BROWN, Sammy, K.
AVERY, George, E.
WIGGIN, Andrew, K.
BEAL, Samuel, W.
Title: INTEGRATED CIRCUITS PACKAGING SYSTEM AND METHOD
Abstract:
A plurality of integrated circuits are efficiently interconnected to improve the electrical performance of the overall system (20). This is accomplished by providing high speed, high density, system level interconnect, including interchip routing lines, on the integrated circuit devices (10), thereby reducing the routing complexity of the substrate or board (14). The devices are mounted directly on the board (14). An integrated cncuit deb vice comprises an integrated circuit region including integrated circuit elements. An interconnect layer (25) includes an insulative material, a plurality of conductive traces, and a plurality of conductive bond pads (22) arranged in first and second subsets. A first subgroup of the conductive traces (20) are connected to the integrated circuit elements in the integrated circuit region and are connected to the first subset of conductive bond pads (22). A second subgroup of the conductive traces (20) are electrically insulated from the integrated circuit elements and are electrically insulated from the first subgroup of the conductive traces to form a pass through (25). The second subgroup of the conductive traces (20) are connected to the second subset of conductive bond pads (22).