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Machine translation
1. (WO2001089167) METHOD AND SYSTEM FOR OVERLOADED ARRAY PROCESSING
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2001/089167    International Application No.:    PCT/US2001/015521
Publication Date: 22.11.2001 International Filing Date: 14.05.2001
Chapter 2 Demand Filed:    06.11.2001    
IPC:
H04B 7/08 (2006.01)
Applicants: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC. [US/US]; 1872 Pratt Drive Suite 1625 Blacksburg, VA 24060 (US) (For All Designated States Except US).
HICKS, James, E. [US/US]; (US) (For US Only).
BOYLE, Robert, J. [US/US]; (US) (For US Only).
BAYRAM, Saffet [CY/US]; (US) (For US Only).
REED, Jeffrey, H. [US/US]; (US) (For US Only)
Inventors: HICKS, James, E.; (US).
BOYLE, Robert, J.; (US).
BAYRAM, Saffet; (US).
REED, Jeffrey, H.; (US)
Agent: MEIER, Harold, E.; Baker Botts LLP Suite 600 2001 Ross Ave. Dallas, TX 75201-2980 (US)
Priority Data:
60/204,117 15.05.2000 US
Title (EN) METHOD AND SYSTEM FOR OVERLOADED ARRAY PROCESSING
(FR) PROCEDE ET SYSTEME DE TRAITEMENT MATRICIEL EN SURCHARGE
Abstract: front page image
(EN)According to the present invention, a method and system for array processing are disclosed. Signals transmitting a symbol set are received. A dominant signal set for each signal, which includes dominant signals that interfere with the signal, is determined. A trellis, which includes paths that represent possible symbol sets, is constructed from the dominant signal sets. An optimal path from the trellis is selected, and the symbol set represented by the optimal path is determined.
(FR)L'invention concerne un procédé et un système de traitement matriciel. Des signaux transmettant un ensemble de symboles sont reçus. Un ensemble de signaux dominants est déterminé pour chaque signal, comprenant des signaux dominants interférant avec le signal. Un treillis, comportant des voies qui représentent des ensembles de symboles possibles, est constitué à partir des ensembles de signaux dominants. Une voie optimale est sélectionnée dans le treillis et l'ensemble de symboles représenté par la voie optimale est déterminé.
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EC, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)