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Machine translation
1. (WO2001088986) STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2001/088986    International Application No.:    PCT/US2001/014130
Publication Date: 22.11.2001 International Filing Date: 01.05.2001
Chapter 2 Demand Filed:    10.12.2001    
IPC:
H01L 21/8246 (2006.01), H01L 27/115 (2006.01)
Applicants: ADVANCED MICRO DEVICES, INC. [US/US]; One AMD Place Mail Stop 68 Sunnyvale, CA 94088-3453 (US)
Inventors: RANDOLPH, Mark, W.; (US).
HOLLMER, Shane, Charles; (US).
CHEN, Pau-Ling; (US).
FASTOW, Richard, M.; (US)
Agent: RODDY, Richard, J.; Advanced Micro Devices, Inc. One AMD Place Mail Stop 68 Sunnyvale, CA 94088-3453 (US).
WRIGHT, HUGH. R.; BROOKES BATCHELLOR 102-108 Clerkenwell Road London EC1M 5SA (GB)
Priority Data:
60/204,406 16.05.2000 US
09/721,031 22.11.2000 US
Title (EN) STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
(FR) BRIDAGE DECALE DE LIGNES BINAIRES D'UNE CELLULE DE MEMOIRE NON VOLATILE
Abstract: front page image
(EN)An array of memory cells that includes a plurality of memory cells interconnected via a grid of wordlines and bitlines (224), wherein each of the bitlines (224) is buried. The array further includes a plurality of contacts (228), wherein each of the plurality of contacts (228) is formed every N wordlines, N=1,2,3, ..., and wherein each of the plurality of contacts (228) overlies a gate (229) of a different one of the plurality of memory cells. A strap (230) connects one of the buried bitlines (224) to a gate (229) that underlies one of the plurality of contacts (228) and wherein a column of the bitlines has a first discontinuous and a second discontinuous bitline (224) that are separated from one another by a distance $g(D).
(FR)L'invention concerne un réseau qui comprend plusieurs cellules de mémoire reliées par une grille de lignes de mots et lignes binaires (224). Chacune des lignes binaires (224) est enterrée. Le réseau comprend en outre plusieurs bornes (228), chacune étant formée toutes les N lignes de mots, N étant égal à 1, 2, 3, Chaque borne (228) recouvre une porte (229) d'une cellule de mémoire différente. Une bride (230) relie une des lignes binaires (224) enterrées à une porte (229) qui se trouve sous l'une des bornes (228), une colonne de lignes binaires présentant une première et une seconde lignes binaires discontinues (224), séparées l'une de l'autre d'une longueur $g(D).
Designated States: AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CO, CR, CU, CZ, DE, DK, DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW.
African Regional Intellectual Property Organization (GH, GM, KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM)
European Patent Office (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)