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1. WO2001063398 - DIGITAL SIGNAL PROCESSOR WITH COUPLED MULTIPLY-ACCUMULATE UNITS

Publication Number WO/2001/063398
Publication Date 30.08.2001
International Application No. PCT/US2001/005869
International Filing Date 23.02.2001
Chapter 2 Demand Filed 21.08.2001
IPC
G06F 7/544 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
544for evaluating functions by calculation
CPC
G06F 7/00
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
G06F 7/5443
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
7Methods or arrangements for processing data by operating upon the order or content of the data handled
38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
544for evaluating functions by calculation
5443Sum of products
Applicants
  • QUALCOMM INCORPORATED [US]/[US]
Inventors
  • SIH, Gilbert, C.
  • CHEN, Xufeng
  • HSU, De, D.
Agents
  • OGROD, Gregory, D.
Priority Data
09/513,98026.02.2000US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) DIGITAL SIGNAL PROCESSOR WITH COUPLED MULTIPLY-ACCUMULATE UNITS
(FR) PROCESSEUR DE SIGNAL NUMERIQUE COMPRENANT DES MULTIPLICATEURS-ACCUMULATEURS COUPLES
Abstract
(EN) Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C) + (D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.
(FR) Selon l'invention, deux multiplicateurs-accumulateurs sont couplés de sorte que le calcul (B*C)+(D*E) puisse s'effectuer en un cycle. Un additionneur (216) additionne les produits des deux multiplicateurs (260), (208). La somme de ces multiplicateurs est appliquée au premier accumulateur (220). De préférence, le second produit est également appliqué au second accumulateur (222) et un multiplexeur (128) applique soit un zéro, soit le second produit à l'additionneur (216). Si deux calculs indépendants doivent être effectués simultanément, c'est le zéro qui est appliqué et la sortie du second accumulateur est retournée à la pile de registres (PI2). Si un seul calcul (B*C) + (D*E) doit être effectué, c'est le second produit qui est appliqué à l'additionneur et la sortie du second accumulateur n'est pas prise en compte.
Related patent documents
ININ/PCT/2002/1325/CHEThis application is not viewable in PATENTSCOPE because the national phase entry has not been published yet or the national entry is issued from a country that does not share data with WIPO or there is a formatting issue or an unavailability of the application.
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