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1. WO2001056082 - AUTO-ALIGNING POWER TRANSISTOR PACKAGE

Publication Number WO/2001/056082
Publication Date 02.08.2001
International Application No. PCT/US2001/002167
International Filing Date 22.01.2001
Chapter 2 Demand Filed 22.08.2001
IPC
H01L 23/13 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
13characterised by the shape
H01L 23/544 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
544Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 23/66 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for
64Impedance arrangements
66High-frequency adaptations
CPC
H01L 2223/54473
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2223Details relating to semiconductor or other solid state devices covered by the group H01L23/00
544Marks applied to semiconductor devices or parts
54473for use after dicing
H01L 2223/6644
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2223Details relating to semiconductor or other solid state devices covered by the group H01L23/00
58Structural electrical arrangements for semiconductor devices not otherwise provided for
64Impedance arrangements
66High-frequency adaptations
6644Packaging aspects of high-frequency amplifiers
H01L 2224/48091
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
48of an individual wire connector
4805Shape
4809Loop shape
48091Arched
H01L 2224/49175
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
47Structure, shape, material or disposition of the wire connectors after the connecting process
49of a plurality of wire connectors
491Disposition
4912Layout
49175Parallel arrangements
H01L 23/13
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
13characterised by the shape
H01L 23/544
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
544Marks applied to semiconductor devices ; or parts; , e.g. registration marks, ; alignment structures, wafer maps
Applicants
  • ERICSSON INC. [US]/[US]
Inventors
  • HOYER, Henrik, I.
  • LEIGHTON, Larry
  • MOLLER, Thomas, W.
  • HUME, Jeff
Agents
  • BURSE, David, T.
  • VON FISCHERN, Bernhard
Priority Data
09/493,29528.01.2000US
09/493,29728.01.2000US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) AUTO-ALIGNING POWER TRANSISTOR PACKAGE
(FR) BOITIER DE TRANSISTOR A ALIGNEMENT AUTOMATIQUE
Abstract
(EN) An LDMOS power package includes a mounting substrate having a surface comprising one or more alignment elements, e.g., an etched marker line, raised abutment, or a trough, to provide for uniform positioning of semiconductor elements, e.g., the transistor die and matching input and output capacitors, in a large scale production. In one embodiment, the power package includes a conductive mounting flange having a surface, the flange surface comprising a plurality of alignment elements. An input matching capacitor is attached to the flange surface proximate a first alignment element. A semiconductor die having a plurality of transistor elements is attached to the flange surface proximate a second alignment element. An output matching capacitor is attached to the flange surface proximate a third alignment element.
(FR) Boîtier de transistor (LDMOS) comprenant un substrat de montage dont la surface présente un ou plusieurs éléments d'alignement, notamment une ligne de marquage gravée, une butée surélevée ou un évidement permettant de placer de façon uniforme des éléments semi-conducteurs, par exemple, la matrice du transistor et des condensateurs appariés d'entrée et de sortie, produits sur une échelle importante. Dans un mode de réalisation, ce boîtier comporte une bride de montage conductrice possédant une surface présentant une pluralité d'éléments d'alignement. Un condensateur correspondant d'entrée est fixé à la surface de la bride à proximité d'un premier élément d'alignement. Une matrice semi-conductrice possédant une pluralité d'éléments de transistor est fixée à la surface de la bride à proximité d'un deuxième élément d'alignement. Un condensateur correspondant de sortie est fixé à la surface de la bride à proximité d'un troisième élément d'alignement.
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