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1. WO2001056075 - NITRIDATION BARRIERS FOR NITRIDATED TUNNEL OXIDE FOR CIRCUITRY FOR FLASH MEMORY TECHNOLOGY AND FOR LOCOS/STI ISOLATION

Publication Number WO/2001/056075
Publication Date 02.08.2001
International Application No. PCT/US2000/034213
International Filing Date 13.12.2000
Chapter 2 Demand Filed 19.07.2001
IPC
H01L 21/762 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
76Making of isolation regions between components
762Dielectric regions
H01L 21/8239 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
CPC
H01L 21/762
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
762Dielectric regions ; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
H01L 21/76202
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
762Dielectric regions ; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
76202using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
H01L 21/76224
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
76Making of isolation regions between components
762Dielectric regions ; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
76224using trench refilling with dielectric materials
H01L 27/1052
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
1052Memory structures and multistep manufacturing processes therefor not provided for in groups H01L27/1055 - H01L27/112
Y10S 438/981
YSECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
10TECHNICAL SUBJECTS COVERED BY FORMER USPC
STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
438Semiconductor device manufacturing: process
981Utilizing varying dielectric thickness
Applicants
  • ADVANCED MICRO DEVICES, INC. [US]/[US]
Inventors
  • PHAM, Tuan, Duc
  • RAMSBEY, Mark, T.
  • SUN, Yu
  • CHANG, Chi
Agents
  • RODDY, Richard, J.
Priority Data
09/491,45726.01.2000US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) NITRIDATION BARRIERS FOR NITRIDATED TUNNEL OXIDE FOR CIRCUITRY FOR FLASH MEMORY TECHNOLOGY AND FOR LOCOS/STI ISOLATION
(FR) BARRIERES DE NITRURATION D'OXYDE TUNNEL NITRURE POUR CIRCUITS UTILISES DANS LA TECHNOLOGIE DES MEMOIRES FLASH ET DE L'ISOLATION LOCOS/PAR TRANCHEES PEU PROFONDES
Abstract
(EN) An improved flash memory device, which has shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.
(FR) L'invention concerne un dispositif à mémoire flash amélioré, qui comporte une isolation par tranchées peu profondes dans la région périphérique et une isolation LOCOS dans la région noyau. Un masque dur est d'abord utilisé pour créer l'isolation par tranchées peu profondes. L'isolation LOCOS est ensuite réalisée. Le décapage permet alors d'éliminer les inclusions. La mémoire flash peut utiliser une isolation par tranchées peu profondes pour limiter l'empiètement. Elle peut en outre comporter une couche d'oxyde tunnel nitrurée. Un masque dur est utilisé pour empêcher une contamination au nitrure de la couche d'oxyde de grille.
Related patent documents
SGSG2002042422This application is not viewable in PATENTSCOPE because the national phase entry has not been published yet or the national entry is issued from a country that does not share data with WIPO or there is a formatting issue or an unavailability of the application.
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