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1. WO2001056063 - THINNING AND DICING OF SEMICONDUCTOR WAFERS USING DRY ETCH, AND OBTAINING SEMICONDUCTOR CHIPS WITH ROUNDED BOTTOM EDGES AND CORNERS

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Publication Number WO/2001/056063
Publication Date 02.08.2001
International Application No. PCT/US2001/002544
International Filing Date 25.01.2001
Chapter 2 Demand Filed 16.08.2001
IPC
H01L 21/301 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301to subdivide a semiconductor body into separate parts, e.g. making partitions
H01L 21/3065 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
3065Plasma etching; Reactive-ion etching
H01L 21/44 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
44Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428158
H01L 23/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
02Containers; Seals
CPC
H01L 21/78
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
H01L 2224/16
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
15Structure, shape, material or disposition of the bump connectors after the connecting process
16of an individual bump connector
H01L 2224/45144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
42Wire connectors; Manufacturing methods related thereto
44Structure, shape, material or disposition of the wire connectors prior to the connecting process
45of an individual wire connector
45001Core members of the connector
45099Material
451with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
45138the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
45144Gold (Au) as principal constituent
H01L 2924/10158
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
10Details of semiconductor or other solid state devices to be connected
1015Shape
10155being other than a cuboid
10158at the passive surface
Applicants
  • TRU-SI TECHNOLOGIES, INC. [US]/[US]
Inventors
  • SINIAGUINE, Oleg
  • HALAHAN, Patrick
  • SAVASTIOUK, Sergey
Agents
  • Michael Shenker, Esq.
Priority Data
09/491,45626.01.2000US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) THINNING AND DICING OF SEMICONDUCTOR WAFERS USING DRY ETCH, AND OBTAINING SEMICONDUCTOR CHIPS WITH ROUNDED BOTTOM EDGES AND CORNERS
(FR) AMINCISSEMENT ET DECOUPE DE PLAQUETTES DE SEMICONDUCTEURS PAR ATTAQUE A SEC, ET OBTENTION DE PUCES DE SEMICONDUCTEURS A BORDS ET A COINS INFERIEURS ARRONDIS
front page image
Abstract
(EN)
A semiconductor wafer (210) is diced before thinning. The wafer (210) is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then, the wafer is placed into a non-contact wafer holder (510), and the wafer backside is blanket etched with a dry etch, for example, atmospheric pressure plasma etch. The wafer is thinned until the grooves are exposed from the backside. The dry etch leaves the chip's backside smooth. After the grooves have been exposed, the dry etch is continued to remove damage from the chip sidewalls and to round the chip's bottom edges (110E) and corners (110C). As a result, the chip becomes more reliable, and in particular more resistant to thermal and other stresses.
(FR)
Selon le procédé de l'invention, la plaquette en semiconducteur est découpée en puces avant l'amincissement. Ladite plaquette n'est découpée que sur une partie de son épaisseur, de manière à former des rainures d'une profondeur au moins égale à l'épaisseur final de chacune des puces que l'on souhaite obtenir à partir de la plaquette. Ensuite, la plaquette est disposée dans un porte-plaquette sans contact, et le dos de la plaquette est gravé par attaque à sec, notamment par attaque au plasma sous pression atmosphérique. La plaquette est amincie jusqu'à ce que les rainures apparaissent sur le dos de la plaquette. L'attaque à sec laisse le dos de la puce lisse. Après l'apparition des rainures, on poursuit l'attaque à sec de manière à éliminer tout défaut au niveau des parois latérales de la puce et à arrondir les côtés et les coins inférieurs des puces. Ainsi, on obtient une puce plus fiable, et notamment plus résistante aux contraintes thermiques ou autres.
Also published as
EP1266399
JP2003521120
Latest bibliographic data on file with the International Bureau
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