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1. (WO2001048800) SEMICONDUCTOR WAFER PROCESSING APPARATUS AND PROCESSING METHOD
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2001/048800 International Application No.: PCT/JP2000/009183
Publication Date: 05.07.2001 International Filing Date: 25.12.2000
IPC:
C23C 18/16 (2006.01) ,C25D 7/12 (2006.01) ,C25D 17/12 (2006.01) ,C25D 17/14 (2006.01) ,H01L 21/00 (2006.01) ,H01L 21/288 (2006.01) ,H01L 21/768 (2006.01) ,H05K 3/42 (2006.01)
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
18
Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
16
by reduction or substitution, i.e. electroless plating
C CHEMISTRY; METALLURGY
25
ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
D
PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; JOINING WORKPIECES BY ELECTROLYSIS; APPARATUS THEREFOR
7
Electroplating characterised by the article coated
12
Semiconductors
C CHEMISTRY; METALLURGY
25
ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
D
PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; JOINING WORKPIECES BY ELECTROLYSIS; APPARATUS THEREFOR
17
Constructional parts, or assemblies thereof, of cells for electrolytic coating
10
Electrodes
12
Shape or form
C CHEMISTRY; METALLURGY
25
ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
D
PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; JOINING WORKPIECES BY ELECTROLYSIS; APPARATUS THEREFOR
17
Constructional parts, or assemblies thereof, of cells for electrolytic coating
10
Electrodes
14
for pad-plating
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
283
Deposition of conductive or insulating materials for electrodes
288
from a liquid, e.g. electrolytic deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
40
Forming printed elements for providing electric connections to or between printed circuits
42
Plated through-holes
Applicants:
KIMURA, Norio [JP/JP]; JP (UsOnly)
MISHIMA, Koji [JP/JP]; JP (UsOnly)
KUNISAWA, Junji [JP/JP]; JP (UsOnly)
ODAGAKI, Mitsuko [JP/JP]; JP (UsOnly)
MAKINO, Natsuki [JP/JP]; JP (UsOnly)
TSUJIMURA, Manabu [JP/JP]; JP (UsOnly)
INOUE, Hiroaki [JP/JP]; JP (UsOnly)
NAKAMURA, Kenji [JP/JP]; JP (UsOnly)
MATSUMOTO, Moriji [JP/JP]; JP (UsOnly)
MATSUDA, Tetsuo [JP/JP]; JP (UsOnly)
KANEKO, Hisashi [JP/JP]; JP (UsOnly)
MORITA, Toshiyuki [JP/JP]; JP (UsOnly)
HAYASAKA, Nobuo [JP/JP]; JP (UsOnly)
OKUMURA, Katsuya [JP/JP]; JP (UsOnly)
EBARA CORPORATION [JP/JP]; 11-1, Haneda Asahi-cho Ohta-ku, Tokyo 144-8510, JP (AllExceptUS)
KABUSHIKI KAISHA TOSHIBA [JP/JP]; 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa 210-8520, JP (AllExceptUS)
Inventors:
KIMURA, Norio; JP
MISHIMA, Koji; JP
KUNISAWA, Junji; JP
ODAGAKI, Mitsuko; JP
MAKINO, Natsuki; JP
TSUJIMURA, Manabu; JP
INOUE, Hiroaki; JP
NAKAMURA, Kenji; JP
MATSUMOTO, Moriji; JP
MATSUDA, Tetsuo; JP
KANEKO, Hisashi; JP
MORITA, Toshiyuki; JP
HAYASAKA, Nobuo; JP
OKUMURA, Katsuya; JP
Agent:
WATANABE, Isamu ; GOWA Nishi-Shinjuku 4F 5-8, Nishi-Shinjuku 7-chome Shinjuku-ku, Tokyo 160-0023, JP
Priority Data:
11/36775424.12.1999JP
2000/11986120.04.2000JP
2000/12184121.04.2000JP
2000/13187928.04.2000JP
2000/13201501.05.2000JP
2000/15375424.05.2000JP
2000/16580102.06.2000JP
2000/24435511.08.2000JP
2000/31269512.10.2000JP
2000/6545909.03.2000JP
Title (EN) SEMICONDUCTOR WAFER PROCESSING APPARATUS AND PROCESSING METHOD
(FR) PROCEDE ET APPAREIL DE TRAITEMENT DE TRANCHE DE SEMI-CONDUCTEUR
Abstract:
(EN) A semiconductor wafer processing apparatus and processing method, in which a circuit pattern groove and/or hole formed in a semiconductor wafer is filled with a metal plating film and the metal plating film is removed except for the portion in the groove/hole so as to fabricate circuit wiring. The semiconductor wafer processing apparatus comprises a load/unload unit (1) for loading/unloading a semiconductor wafer (W) in a dried state on which a circuit is fabriacated, a film forming unit (2) for forming a metal plating film on the loaded semiconductor wafer, a bevel-etching unit (116) for etching the peripheral part of the semiconductor wafer, polishing units (10, 11) for polishing at least a part of the metal plating film on the semiconductor wafer, and robots (3, 8) for transferring the semiconductor wafer between the units.
(FR) La présente invention concerne un appareil de traitement de tranche de semiconducteur, dans lequel une rainure dessinant un motif de circuit et/ou un trou formé dans la tranche d'un semiconducteur contient un film de placage métallique, ce film étant ensuite enlevé de partout à l'exception de la partie rainure/trou de manière à fabriquer un circuit de câblages. L'appareil de traitement de la tranche de semiconducteur comprend une unité de chargement/déchargement (1) pour charger/décharger une tranche de semiconducteur (W) à l'état sec sur laquelle est fabriqué un circuit, une unité filmogène (2) pour former un film de placage métallique sur la tranche de semiconducteur chargée, une unité de gravure en biseau (116) pour graver la partie périphérique de la tranche de semiconducteur, des unités de polissage (10, 11) pour polir au moins une partie du film de placage métallique sur la tranche de semiconducteur, et enfin, des robots (3, 8) pour transférer la tranche de semiconducteur entre les unités.
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Designated States: CN, KR, US
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)