WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Options
Query Language
Stem
Sort by:
List Length
Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2001039265) TOP GATE THIN-FILM TRANSISTOR AND METHOD OF PRODUCING THE SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2001/039265 International Application No.: PCT/EP2000/010904
Publication Date: 31.05.2001 International Filing Date: 02.11.2000
IPC:
H01L 21/336 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants: KONINKLIJKE PHILIPS ELECTRONICS N.V.[NL/NL]; Groenewoudseweg 1 NL-5621 BA Eindhoven, NL
Inventors: BATTERSBY, Stephen, J.; NL
Agent: SHARROCK, Daniel, J.; Internationaal Octrooibureau B.V. Prof. Holstlaan 6 NL-5656 AA Eindhoven, NL
Priority Data:
9927287.419.11.1999GB
Title (EN) TOP GATE THIN-FILM TRANSISTOR AND METHOD OF PRODUCING THE SAME
(FR) TRANSISTOR A FILM MINCE A PORTE SUPERIEURE ET PROCEDE DE FABRICATION CORRESPONDANT
Abstract:
(EN) A method of producing a top gate thin-film transistor comprises the steps of forming doped silicon source and drain regions (6a, 8a) on an insulating substrate (2) and subjecting the face of the substrate (2) on which the source and drain regions (6a, 8a) are formed to plasma treatment to form a doped surface layer. An amorphous silicon layer (12) is formed on the doped surface layer over at least the spacing between the source and drain regions (6a, 8a) and an insulated gate structure (14, 16) is formed over the amorphous silicon layer (12). Laser annealing of areas of the amorphous silicon layer not shielded by the gate conductor is carried out to form polysilicon portions (12a, 12b) having the impurities diffused therein. In the method of the invention, doped silicon source and drain regions underlie the silicon layer to be crystallized using the laser annealing process. It has been found that the laser annealing process can then result in crystallization of the full thickness of the amorphous silicon layer. This results from the similar thermal properties of the doped source and drain regions and the silicon layer defining the main body of the transistor.
(FR) Selon l'invention, le procédé de fabrication d'un transistor à film mince à porte supérieure consiste à former des régions source et drain dopées en silicium (6a, 8a) sur un substrat isolant (2) et à soumettre la face du substrat (2) sur laquelle sont formées les régions sources et drain (6a, 8a) au traitement au plasma, de manière à former une couche en surface dopée. Une couche de silicium amorphe (12) est formée sur la couche en surface dopée par-dessus au moins un espacement entre les régions de source et de drain (6a, 8a), et une structure de porte isolée (14, 16) est formée par-dessus la couche de silicium amorphe (12). On procède à la recuisson au laser des zones de la couche de silicium amorphe non protégées par le conducteur de porte de manière à former des parties de polysilicium (12a, 12b) comportant des impuretés diffusées. Selon le procédé, les régions source et drain dopées en silicium se trouvent sous la couche de silicium destinée à être cristallisée au moyen du procédé de recuisson au laser. On a découvert que la recuisson au laser peut conduire à la cristallisation de la couche de silicium amorphe sur toute l'épaisseur. Cela découle des propriétés thermique similaires des régions source et drain dopées et de la couche de silicium délimitant le corps principal du transistor.
front page image
Designated States: JP, KR
European Patent Office (EPO) (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE, TR)
Publication Language: English (EN)
Filing Language: English (EN)