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1. WO2001039251 - HIGH PERFORMANCE OUTPUT BUFFER WITH ESD PROTECTION

Publication Number WO/2001/039251
Publication Date 31.05.2001
International Application No. PCT/US2000/032006
International Filing Date 22.11.2000
Chapter 2 Demand Filed 21.06.2001
IPC
H01L 27/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/118 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
118Masterslice integrated circuits
CPC
H01L 27/0266
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
0203Particular design considerations for integrated circuits
0248for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
0251for MOS devices
0266using field effect transistors as protective elements
H01L 27/11898
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
118Masterslice integrated circuits
11898Input and output buffer/driver structures
H01L 2924/0002
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2924Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
0001Technical content checked by a classifier
0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applicants
  • HONEYWELL INC. [US]/[US]
Inventors
  • FECHNER, Paul, S.
Agents
  • HOIRIIS, David
  • CRISS, Roger H.
Priority Data
09/449,31224.11.1999US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) HIGH PERFORMANCE OUTPUT BUFFER WITH ESD PROTECTION
(FR) TAMPON DE SORTIE HAUTES PERFORMANCES AVEC PROTECTION CONTRE LES DECHARGES ELECTROSTATIQUES
Abstract
(EN)
An output buffer with built-in ESD protection is disclosed. The built-in ESD protection is preferably formed using transistors from the sea-of-transistors or sea-of-gates region (14) of an integrated circuit, which may eliminate the need for dedicated ESD devices, and in particular, dedicated ESD devices that are pre-fabricated into the under-layers in and around the perimeter region (18) of the integrated circuit.
(FR)
Cette invention concerne un tampon de sortie avec protection intégrée contre les décharges électrostatiques. Cette protection intégrée se présente de préférence sous forme de transistors pris dans la région de prédiffusés (14) d'un circuit intégré, ce qui rend superflu l'emploi de dispositifs de protection spécifiques contre les décharges électrostatiques, et en particulier de dispositifs préfabriqués noyés dans les sous-couches et dans la zone périphérique (18) du circuit intégré.
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