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1. (WO2001039194) SINGLE-EVENT UPSET HARDENED RECONFIGURABLE BI-STABLE CMOS LATCH

Pub. No.:    WO/2001/039194    International Application No.:    PCT/US2000/001356
Publication Date: Fri Jun 01 01:59:59 CEST 2001 International Filing Date: Fri Jan 21 00:59:59 CET 2000
IPC: G11C 5/00
G11C 8/20
G11C 11/412
Applicants: LOCKHEED MARTIN CORPORATION
Inventors: ROCKETT, Leonard, R.
Title: SINGLE-EVENT UPSET HARDENED RECONFIGURABLE BI-STABLE CMOS LATCH
Abstract:
The present invention provides a single-event upset (SEU) hardened integrated circuit (20, 100, 120). The integrated circuit includes an SEU hardened asymmetric bi-stable CMOS latch (22, 22A, 22B) having a first logic state (82, 84) and a second logic state (86, 88). A supply voltage (80) is operably coupled to the asymmetric bi-stable latch (22, 22A, 22B), where upon activation of the supply voltage (80) the asymmetric bi-stable latch (22, 22A, 22B) is always set to the first logic state (82, 84). A switch (36) may be provided for changing the latch (22, 22A, 22B) from the first logic state (82, 84) to the second logic state (86, 88).